W66910 Datasheet, PDF (76/81 Pages) Winbond – TE Mode ISDN S/T-Controller with Microprocessor Interface

Data Sheet
W66910 PCI ISDN S/T-Controller
Parameter
ta1
ta2
ta3
ta4
ta5
ta6
ta7
ta8
Parameter Descriptions
PBCK pulse high
PBCK pulse low
Frame clock asserted from
PBCK
PTXD data delay from PBCK
Frame clock deasserted from
PBCK
PTXD hold time from PBCK
PRXD setup time to PBCK
PRXD hold time from PBCK
Min.
195
10
20
10
Nominal
325
325
Max.
455
20
20
20
Remarks
Unit = ns
Note : The PCM clocks are locked to the S/T receive clock. At every two or three PCM frame time (125 µs), PBCK and PFCK1,
PFCK2 may be adjusted by one local oscillator cycle (130 ns) in order to synchronize with S/T clock. This shift is made on the
LOW level time of PBCK and the HIGH level time is not affected. This introduces jitters on the PBCK, PFCK1 and PFCK2 with
jitter amplitude 260 ns (peak-to-peak) and jitter frequency about 2.67~4 kHz.
9.4.2 8-bit Microprocessor Timing
Intel mode read cycle timing
t1
ALE
AD<7:0>
CS#
RD#
t2 t3
A<7:0>
t6
t4
t10
t9
D<7:0>
t8
t7
t5
A<7:0>
t11
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Publication Release Date: Feb,2001
Revision 1.0