W66910 Datasheet, PDF (69/81 Pages) Winbond – TE Mode ISDN S/T-Controller with Microprocessor Interface

Data Sheet
W66910 PCI ISDN S/T-Controller
8.2.6 B1_ch Extended Interrupt Mask Register B1_EXIM Read/Write Address 25H
Value after reset: FFH
7
6
5
4
3
RMR RME RDOV
2
1
0
XFR XDUN
Setting the bit to "1" masks the corresponding interrupt source in B1_EXIR register. Masked interrupt status bits are read as zero
when B1_EXIR register is read. They are internally stored and pending until the mask bits are zero.
All the interrupts in B1_EXIR will be masked if the IMASK : B1_EXI bit is set to "1".
8.2.7 B1_ch Status Register B1_STAR Read
Address 26H
Value after reset: 20H
7
6
5
4
RDOV CRCE RMB
3
2
1
XDOW
0
XBZ
RDOV Receive Data Overflow
A "1" indicates that the receive FIFO is overflow. The incoming data overwrote data in the receive FIFO. The overflow condition
will set both the status and interrupt bits. It is recommended that software must read the RDOV bit after reading data from
receive FIFO at RMR or RME interrupt. The software must abort the data and issue a RRST command to reset the receiver if
RDOV=1.
CRCE CRC Error
Used in transparent mode only. This bit indicates the result of frame CRC check:
0 : CRC correct
1 : CRC incorrect
RMB Receive Message Aborted
Used in transparent mode only. A "1" means that a sequence of ≥seven 1's was received and the frame is aborted by the
B1_HDLC controller. Software must issue RRST command to reset the receiver.
Note : Bit CRCE is valid only after a RME interrupt and remains valid until the frame is acknowledged via RACK command.
RMB must be polled after a RMR/RME interrupt.
XDOW Transmit Data Overwritten
At least one byte of data has been overwritten in the B1_XFIFO.This bit is cleared only by XRST command.
XBZ Transmitter Busy
The B1_HDLC transmitter is busy when XBZ is read as "1". This bit may be polled. The XBZ bit is active when an XMS
command was issued and the message has not been completely transmitted.
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Publication Release Date: Feb,2001
Revision 1.0