W66910 Datasheet, PDF (42/81 Pages) Winbond – TE Mode ISDN S/T-Controller with Microprocessor Interface

Data Sheet
8. REGISTER DESCRIPTIONS
W66910 PCI ISDN S/T-Controller
Note : For all the internal registers, only byte access is allowed in all cases.
8.1 Chip Control and D_ch HDLC controller
TABLE 8.1 REGISTER ADDRESS MAP: CHIP CONTROL AND D CHANNEL HDLC
Section Offset
8.1.1 00
8.1.2 01
8.1.3 02
8.1.4 03
8.1.5 04
8.1.6 05
8.1.7 06
8.1.8 07
8.1.9 08
8.1.10 09
8.1.11 0A
8.1.12 0B
8.1.13 0C
8.1.14 0D
8.1.15 0E
8.1.16 0F
8.1.17 10
8.1.18 11
8.1.19 12
8.1.20 13
8.1.21 14
8.1.22 15
8.1.23 16
8.1.24 17
8.1.25 18
8.1.26 19
8.1.27 1A
8.1.28 1B
8.1.29 1C
8.1.30 1D
8.1.31 1E
Access Register Name
R D_RFIFO
W D_XFIFO
W D_CMDR
R/W D_MODE
R/W TIMR1
R_clear ISTA
R/W IMASK
R_clear D_EXIR
R/W D_EXIM
R D_XSTA
R D_RSTA
R/W D_SAM
R/W D_SAP1
R/W D_SAP2
R/W D_TAM
R/W D_TEI1
R/W D_TEI2
R D_RBCH
R D_RBCL
R/W TIMR2
R/W L1_RC
R/W CTL
R CIR
R/W CIX
R SQR
R/W SQX
R/W PCTL
R MO0R
R/W MO0X
R_clear MO0I
R/W MO0C
Description
D channel receive FIFO
D channel transmit FIFO
D channel command register
D channel mode control
Timer 1
Interrupt status register
Interrupt mask register
D channel extended interrupt
D channel extended interrupt mask
D channel transmit status
D channel receive status
D channel address mask 1
D channel individual SAPI 1
D channel individual SAPI 2
D channel address mask 2
D channel individual TEI 1
D channel individual TEI 2
D channel receive frame byte count high
D channel receive frame byte count low
Timer 2
GCI layer 1 ready code
Control register
Command/Indication receive
Command/Indication transmit
S/Q channel receive register
S/Q channel transmit register
Peripheral control register
Monitor receive channel 0
Monitor transmit channel 0
Monitor channel 0 interrupt
Monitor channel 0 control register
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Publication Release Date: Feb,2001
Revision 1.0