W66910 Datasheet, PDF (64/81 Pages) Winbond – TE Mode ISDN S/T-Controller with Microprocessor Interface

Data Sheet
W66910 PCI ISDN S/T-Controller
IC2 IC2 Synchronous Transfer Interrupt
When enabled, an interrupt is generated at end of GCI IC2 time slot every GCI frame (125 µs).
CI1 GCI CI1 Synchronous Transfer Interrupt
When enabled, an interrupt is generated when there is a change in the received CIR1_6-1 code without double last look criterion.
8.1.46 GCI Extended Interrupt Mask Register GCI_EXIM Read/Write Address 4BH
Value after reset: F7H
7
6
5
4
3
1
1
1
MO1C
0
2
1
0
IC1
IC2
CI1
Bits 7-5 are fixed at "1" and bit 3 is fixed at '0". This means MO0C interrupt cannot be masked. The interrupt is disabled when
the bit is set.
8.2 B1 HDLC controler
TABLE 8.3 REGISTER ADDRESS MAP: B1 CHANNEL HDLC
Section
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
8.2.6
8.2.7
8.2.8
8.2.9
8.2.10
8.2.11
8.2.12
8.2.13
8.2.14
Offset
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
Access Register Name
R B1_RFIFO
W B1_XFIFO
R/W B1_CMDR
R/W B1_MODE
R_clear B1_EXIR
R/W B1_EXIM
R B1_STAR
R/W B1_ADM1
R/W B1_ADM2
R/W B1_ADR1
R/W B1_ADR2
R B1_RBCL
R B1_RBCH
R/W B1_IDLE
Description
B1 channel receive FIFO
B1 channel transmit FIFO
B1 channel command register
B1 channel mode control
B1 channel extended interrupt
B1 channel extended interrupt mask
B1 channel status register
B1 channel address mask 1
B1 channel address mask 2
B1 channel address 1
B1 channel address 2
B1 channel receive frame byte count low
B1 channel receive frame byte count high
B1 channel transmit idle pattern
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Publication Release Date: Feb,2001
Revision 1.0