W66910 Datasheet, PDF (38/81 Pages) Winbond – TE Mode ISDN S/T-Controller with Microprocessor Interface

Data Sheet
The inter-frame time fill pattern can be programmed to 1's or flags.
W66910 PCI ISDN S/T-Controller
During the frame transmission, the microprocessor reaction time for the XFR interrupt depends on the FIFO threshold setting
and B channel data rate. For example, it is 8 ms if the FIFO threshold is 64 and the B channel data rate is 64 kbps. If the
microprocessor fails to responds within the given reaction time, the transmit FIFO will be underrun. In this case, the W66910
will automatically reset the transmitter and send the inter frame time fill pattern on B channel. The microprocessor is informed
about this via a Transmit Data Underrun interrupt (XDUN bit in Bn_EXIR register). The microprocessor must wait until
transmit FIFO ready (via XFR interrupt), re-write data, and issue XMS command to re-transmit the data.
The microprocessor can abort a frame transmission by issuing a Transmitter Reset command (XRES bit in Bn_CMDR register).
The XRES command resets the transmitter and sends inter frame time fill pattern on B channel. It also results in a transmit pool
ready condition.
Extended transparent mode:
All the data in the transmit FIFO are transmitted without any modification, i.e. no flags and CRCs are inserted, and no bit
stuffing is performed.
Transmission is started by a XMS command. The transmitter requests another block of data via XFR interrupt when more than a
threshold length of vacancies are left in the FIFO. The microprocessor reacts to this condition by writing up to a threshold length
of data into the transmit FIFO and issues a XMS command to continue the message transmission.
The microprocessor reaction time depends on the FIFO threshold setting and B channel data rate. For example, it is 8 ms if the
FIFO threshold is 64 and the B channel data rate is 64 kbps. If the microprocessor fails to respond within the given reaction time,
the transmit FIFO will hold no data to transmit. In this case, the W66910 will automatically reset the transmitter and send idle
channel pattern defined in Bn_IDLE register. The microprocessor is informed about this via a Transmit Data Underrun interrupt
(XDUN bit in Bn_EXIR register). The microprocessor must wait until transmit FIFO ready (via XFR interrupt), re-write data,
and issue XMS command to re-transmit the data.
7.8 GCI Mode Serial Interface Bus
The GCI is a generalization and enchancement of the general purpose, serial interface bus. The channel structure of the GCI
mode is depicted below. The timing is compatible with Siemens’s IOM-2 TE mode.
Channel Structure of the W66910 GCI Mode:
FSC
CH0
CH1
B1
B2 MON0 D C/I0 IC1 IC2
MON1 C/I1
CH2
C/I2
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Publication Release Date: Feb,2001
Revision 1.0