W66910 Datasheet, PDF (58/81 Pages) Winbond – TE Mode ISDN S/T-Controller with Microprocessor Interface

Data Sheet
MDR0 Monitor channel 0 Data Receive
MER0Monitor channel0 End of Reception
MDA0Monitor channel0 Data Acknowledged
The remote end has acknowledged the Monitor byte being transmitted.
MAB0 Monitor channel0 Data Abort
W66910 PCI ISDN S/T-Controller
8.1.31 Monitor Channel 0 Control Register
MO0C
Read/Write Address 1EH
Value after reset: 00H
7
6
5
4
3
2
1
0
0
0
0
0
MRIE0 MRC0 MXIE0 MXC0
MRIE0 Monitor Channel 0 Receive Interrupt Enable
Monitor channel interrupt status MDR0, MER0 generation is enabled (1) or masked (0).
MRC0 MR Bit Control
Determines the value of the MR bit:
0: MR bit always 1. In addition, the MDR0 interrupt is blocked, except for the first byte of a packet (if MRIE0=1).
1: MR internally controlled by the W66910 according to Monitor channel protocol. In addition, the MDR0 interrupt
is enabled for all received bytes according to the Monitor channel protocol (if MRIE0=1).
MXIE0 Monitor channel 0 Transmit Interrupt Enable
Monitor interrupt status MDA0, MAB0 generation is enabled (1) or masked (0).
MXC0 MX bit Control
Determines the value of the MX bit:
0: MX always 1.
1: MX internally controlled by the W66910 according to Monitor channel protocol.
8.1.32 GCI Mode Control/Status Register
GCR Read/Write Address 1FH
Value after reset: 00H
7
6
5
4
3
2
MAC0 MAC1 GACT TLP GRLP SPU
1
0
PD GMODE
MAC0 Monitor Transmit Channel 0 Active (Read Only)
Data transmission is in progress in GCI mode Monitor channel 0.
0: the previous transmission has been terminated. Before starting a transmission, the microprocessor should verify
that the transmitter is inactive.
1: after having written data into the Monitor Transmit Channel 0 (MO0X) register, the microprocessor sets this bit to 1.
This enables the MX bit to go active (0), indicating the presence of valid Monitor channel data (contents of MOX) in
the correspond frame.
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Publication Release Date: Feb,2001
Revision 1.0