W66910 Datasheet, PDF (50/81 Pages) Winbond – TE Mode ISDN S/T-Controller with Microprocessor Interface

Data Sheet
8.1.11 D_ch Receive Status Register
W66910 PCI ISDN S/T-Controller
D_RSTA Read
Address 0AH
Value after reset: 20H
7
6
5
4
3
2
1
0
0 RDOV CRCE RMB
0
0
0
0
RDOV Receive Data Overflow
A "1" indicates that the D_RFIFO is overflow. The incoming data will overwrite data in the receive FIFO. The data overflow
condition will set both the status and interrupt bits. It is recommended that software must read the RDOV bit after reading data
from D_RFIFO at RMR or RME interrupt. The software must abort the data and issue a RRST command to reset the receiver if
RDOV = 1. The frame overflow condition will not set this bit.
CRCE CRC Error
This bit indicates the result of frame CRC check:
0: CRC correct
1: CRC error
RMB Receive Message Aborted
A "1" means that a sequence of seven 1's was received and the frame is aborted. Software must issue RRST command to reset the
receiver.
Note: Normally D_RSTA register should be read by the microprocessor after a D_RME interrupt. The contents of D_RSTA are
valid only after a D_RME interrupt and remain valid until the frame is acknowledged via a RACK bit.
8.1.12D_ch SAPI Address Mask D_SAM Read/Write Address 0BH
Value after reset: 00H
7
6
5
4
3
2
1
0
SAM7 SAM6 SAM5 SAM4 SAM3 SAM2 SAM1 SAM0
This register masks(disables) the first byte address comparison of the incoming frame. If the mask bit is "1" the corresponding bit
comparisons with D_SAP1, D_SAP2 are disabled. Comparison with SAPG is always performed.
Note : For the LAPD frame, the least significant two bits are the C/R bit and EA =0 bit. It is suggested that the comparison with
C/R bit be masked. EA=0 for two octet address frame e.g LAPD, EA=1 for one octet address frame.
8.1.13 D_ch SAPI1 Register D_SAP1 Read/Write Address 0CH
Value after reset: 00H
7
SA17
6
SA16
5
SA15
4
SA14
3
SA13
2
SA12
1
SA11
0
SA10
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Publication Release Date: Feb,2001
Revision 1.0