W66910 Datasheet, PDF (67/81 Pages) Winbond – TE Mode ISDN S/T-Controller with Microprocessor Interface

Data Sheet
W66910 PCI ISDN S/T-Controller
XME Transmit Message End
In transparent mode, setting this bit indicates the end of the whole frame transmission. The B1_ch HDLC controller transmits the
data in FIFO and automatically appends the CRC and the closing flag sequence in transparent mode.
In extended transparent mode, setting this bit stops the B1_XFIFO data transmission.
This bit is write-only. It's auto-clear.
XRST Transmitter Reset
Setting this bit resets the B1_ch HDLC transmitter and clears the B1_XFIFO. The transmitter will send inter frame time fill
pattern on B channel in transparent mode, or idle pattern in extended transparent mode. This command also results in a transmit
FIFO ready condition.
This bit is write only. It's auto-clear.
8.2.4 B1_ch Mode Register B1_MODE Read/Write
Address 23H
Value after reset: 00H
7
MMS
6
5
4
3
2
1
0
ITF EPCM B1_SW1 B1_SW0 SW56 FTS1 FTS0
MMS Message Mode Setting
Determines the message transfer modes of the B1_ch HDLC controller:
0: Transparent mode. In receive direction, address comparison is performed on each frame. The frames with matched address are
stored in B1_RFIFO. Flag deletion, CRC check and zero bit deletion are performed. In transmit direction, the data is transmitted
with flag insertion, zero bit insertion and CRC generation.
1: Extended transparent mode. In receive direction, all data are received and stored in the B1_RFIFO. In transmit direction, all
data in the B1_XFIFO are transmitted without alteration.
ITF Inter-frame Time Fill
Defines the inter-frame time fill pattern in transparent mode.
0 : Mark. The binary value "1" is transmitted.
1 : Flag. This is a sequence of"01111110".
EPCM Enable PCM Transmit/Receive
0 : Disable data transmit/ receive to/from PCM port. The frame synchronization clock PFCK1 is held LOW.
1 : Enable data transmit/ receive to/from PCM port. The frame synchronization clock PFCK1 is active.
B1_SW1-0 B Channel Switching Select
These two bits, along with PXC bit in PCTL register, determine the connection in B1 channel. See section 7.4 for details.
Note: The connection with microprocessor is through HDLC controller. When HDLC connects with layer 1, either transparent or
extended transparent mode can be used. When HDLC connects with PCM port/GCI bus, only extended transparent mode can be
used and the EPCM bit must be set to enable PCM function.
SW56 Switch 56 Traffic
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Publication Release Date: Feb,2001
Revision 1.0