W66910 Datasheet, PDF (66/81 Pages) Winbond – TE Mode ISDN S/T-Controller with Microprocessor Interface

Data Sheet
W66910 PCI ISDN S/T-Controller
When the number of empty locations is equal to or greater than the threshold value, a XFR interrupt is generated. After a XFR
interrupt, up to 64 or 96 bytes of data can be written into this FIFO for transmission.
8.2.3 B1_ch command register B1_CMDR
Read/Write
Address 22H
Value after reset: 00H
7
RACK
6
RRST
5
4
3
RACT XACTB B1_128
K
2
XMS
1
0
XME XRST
RACK Receive Message Acknowledge
After a RMR or RME interrupt, the microprocessor reads out the data in B1_RFIFO, it then sets this bit to explicitly acknowledge
the interrupt.
This bit is write only. It's auto-clear.
RRST Receiver Reset
Setting this bit resets the B1_ch HDLC receiver.
This bit is write-only. It's auto-clear.
RACT Receiver Active
"1": transmitter is active, 64 kHz clock is provided.
"0": transmitter is inactive, clock is LOW to save power.
This bit is read/write. Read operation returns the previously written value.
XACTB Transmitter Active
"0": transmitter is active, 64 kHz clock is provided.
"1": transmitter is inactive, clock is LOW to save power.
This bit is read/write. Read operation returns the previously written value.
B1_128K 128K Mode
"1": Both B1 and B2 channels in layer 1 are combined into single layer 2 channel. The layer 2 B1 channel can operates in
transparent mode or extended transparent mode and layer 2 B2 channel is not used.
"0": Both B1 and B2 channels in layer 1 are not combined.
This bit is read/write. Read operation returns the previously written value.
XMS Transmit Message Start/Continue
In transparent mode, setting this bit initiates the transparent transmission of B1_XFIFO data. The opening flag is automatically
added to the message by the B1_ch HDLC controller. Zero bit insertion is performed on the data. This bit is also used in
subsequent transmission of the frame.
In extended transparent mode, settint this bit activates the transmission of B1_XFIFO data. No flag, CRC or zero bit insertion is
added on the data.
This bit is write-only. It's auto-clear.
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Publication Release Date: Feb,2001
Revision 1.0