W66910 Datasheet, PDF (54/81 Pages) Winbond – TE Mode ISDN S/T-Controller with Microprocessor Interface

Data Sheet
W66910 PCI ISDN S/T-Controller
Note: When SRST = 1, the chip is in reset state. Read or write to any of the registers except SRST bit is inhibited at this time.
OPS1-0 Output Phase Delay Compensation Select1-0
These two bits select the output phase delay compensation.
OPS1 OPS0 Effect
0
0 No output phase delay compensation
0
1 Output phase delay compensation 260ns
1
0 Output phase delay compensation 520 ns
1
1 Output phase delay compensation 1040 ns
8.1.23 Command/Indication Receive Register CIR Read
Address 58H/16H
Value after reset: 0FH
7
6
5
SCC ICC
4
3
2
1
0
CODR3 CODR2 CODR1 CODR0
SCC S Channel Change
A change in the received 4-bit S channel has been detected. The new code can be read from the SQR register. This bit is cleared
via a read of the SQR register.
ICC Indication Code Change
A change in the received indication code has been detected. The new code can be read from the CIR register. This bit is cleared
by a read of the CIR register.
CODR3-0 Layer 1 Indication Code
Value of the received layer 1 indication code. Note these bits have a buffer size of two.
Note : If S/T layer 1 function is disabled and GCI slave mode is enabled (GMODE = 1 in GCR register), CIR register is used to
receive layer 1 indication code from U transceiver. In this case, SCC bit is not used and the supported indication codes are :
Indication
Deactivation confirmation
Power up indication
Symbol
DC
PU
Code
1111
0111
Descriptions
Idle code on GCI interface
U transceiver power up
8.1.24 Command/Indication Transmit Register CIX Read/Write
Value after reset: 0FH
Address 17H
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Publication Release Date: Feb,2001
Revision 1.0