W66910 Datasheet, PDF (45/81 Pages) Winbond – TE Mode ISDN S/T-Controller with Microprocessor Interface

Data Sheet
8.1.3 D_ch command register D_CMDR Write
W66910 PCI ISDN S/T-Controller
Address 02H
Value after reset: 00H
7
6
5
4
3
2
1
0
RACK RRST
0
STT1 XMS
0
XME XRST
RACK Receive Acknowledge
After a D_RMR or D_RME interrupt, the processor must read out the data in D_RFIFO and then sets this bit to acknowledge the
interrupt. Writing “0” to this bit has no effect.
RRST Receiver Reset
Setting this bit resets the D_ch HDLC receiver and clears the D_RFIFO data. Writing “0” to this bit has no effect.
STT1 Start Timer 1
The timer 1 is started when this bit is set to one. The timer is stopped when it expires or by a write of the TIMR1 register.
Writing “0” to this bit has no effect.
XMS Transmit Message Start/Continue
Setting this bit will start or continue the transmission of a frame. The opening flag is automatically added by the HDLC
controller. Writing “0” to this bit has no effect.
XMETransmit Message End
Setting this bit indicates the end of frame transmission.. The D_ch HDLC controller automatically appends the CRC and the
closing flag after the data transmission. Writing “0” to this bit has no effect.
Note: If the frame ≤ 64 bytes, XME plus XMS commands must be issued at the same time.
XRSTTransmitter Reset
Setting this bit resets the D_ch HDLC transmitter and clears the D_XFIFO. The transmitter will send inter frame time fill pattern
(which is 1's) immediately. This command also results in a transmit FIFO ready condition. Writing “0” to this bit has no effect.
8.1.4 D_ch Mode Register D_MODE Read/Write Address 03H
Value after reset : 00H
7
6
5
4
0
RACT XACTB 0
3
2
1
0
0
MFD DLP RLP
RACT Receiver Active
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Publication Release Date: Feb,2001
Revision 1.0