W66910 Datasheet, PDF (49/81 Pages) Winbond – TE Mode ISDN S/T-Controller with Microprocessor Interface

Data Sheet
This bit is set when at least one bit is set in GCI_EXIR register.
W66910 PCI ISDN S/T-Controller
ISC Indication or S Channel Change
A change in the layer 1 indication code or multiframe S channel has been detected. The actual value can be read from CIR or
SQR registers.
T1EXP Timer 1 Expiration
Expiration occurs in the Timer 1.
.
8.1.9 D_ch Extended Interrupt Mask Register D_EXIM
Read/Write Address 08H
Value after reset: FFH
7
6
5
4
3
2
1
0
RDOV XDUN XCOL TIN2 GCI ISC T1EXP 1
Setting the bit to "1" masks the corresponding interrupt source in D_EXIR register. Masked interrupt status bits are read as zero.
They are internally stored and pending until the mask bits are zero.
All the interrupts in D_EXIR will be masked if the IMASK:D_EXI bit is set to "1".
8.1.10 D_ch Transmit Status Register
D_XSTA Read
Address 09H
Value after reset: 00H
7
6
5
4
3
2
1
0
XDOW 0
XBZ DRDY 0
0
0
0
XDOW Transmit Data Overwritten
At least one byte of data has been overwritten in the D_XFIFO. This bit is set by data overwritten condition and is cleared only by
XRST command.
XBZ Transmitter Busy
This bit indicates the D_HDLC transmitter is busy. The XBZ bit is active from the transmission of opening flag to the
transmission of closing flag.
DRDY D Channel Ready
This bit indicates the status of layer 1 D channel.
0: The layer 1 D channel is not ready. No transmission is allowed.
1: The layer 1 D channel is ready. Layer 2 can transmit data to layer 1.
Note : Due to design mistake, DRDY=1 does not mean S/T layer 1 is in F7 state. Software has to check “DRDY=1 and C/I
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Publication Release Date: Feb,2001
Revision 1.0