THS8200-EP Datasheet, PDF (90/104 Pages) Texas Instruments – All-Format Oversampled Component Video/PC Graphics D/A System With Three 11-Bit DACs, CGMS Data Insertion

THS8200-EP
SLES253 – DECEMBER 2009
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
t_H
GY, RCr, BCb data ^{VDD_IO = 1.8 V}
inputs hold time _{VDD_IO = 3.3 V}
t_s
HS_IN, VS_IN, FID
inputs setup time
VDD_IO = 3.3 V⁽²⁾
t_H
HS_IN, VS_IN, FID
inputs hold time
VDD_IO = 3.3 V⁽²⁾
10-bit/20-bit 4:2:2 with CSM, CSC,
t_d(D)
Digital process
delay ⁽³⁾
2x interpolation active
30-bit 4:4:4
VESA clock mode (DLL, CSM, CSC, FIRs bypassed)
ANALOG (DAC) OUTPUTS
DAC resolution
INL
DNL
PSRR
XTALK
K_IMBAL
V_OC
C_O
t_ri
Integral
nonlinearity
Best-fit
VDD_IO = 3.3 V,
CLK = 500 kHz
Video (0.7 + 0.35 V bias)
Generic (1.25 + 0 V bias)
Differential
nonlinearity
VDD_IO = 3.3 V,
CLK = 500 kHz
Video (0.7 + 0.35 V bias)
Generic (1.25 + 0 V bias)
Power supply
ripple rejection
ratio of DAC output
f = dc to 100 kHz⁽⁵⁾
(full scale)
1 MHz sine wave,
offset bias off
1 MHz sine wave,
offset bias on
Crosstalk between
channels ⁽⁶⁾
CLK = 205 MHz, -1 dB sine wave
applied to active channels, offset bias
applied to all channels when turned
on, 37.5 Ω load on all channels
10 MHz sine wave,
offset bias off
10 MHz sine wave,
offset bias on
30 MHz sine wave,
offset bias off
30 MHz sine wave,
offset bias on
Imbalance
between DACs
CLK = 80 MHz⁽⁷⁾
DAC output
compliance voltage R_L = 37.5 Ω⁽⁸⁾
(video only)
Video mode (bias
offset can be added)
Generic mode (bias
offset cannot be added)
DAC output
capacitance (pin
capacitance)
DAC output current
rise time
10 to 90% of full-scale, CLK = 80 MHz
MIN TYP⁽¹⁾
0.5
0.5
1.5
0.5
73 ⁽⁴⁾
33 ⁽⁴⁾
9
10
10
(11 bit (11 bit
internal) internal)
–3
–10
0.2/−0.
3
1/−1
42
49
42
49
42
48
40.5
0.7
1.25
5
3.5
MAX UNIT
nA
nA
nA
pixels
bits
3
LSB
10
1/−1
LSB
1/−1
dB
dB
±2%
0.72
V
1.3
pF
4.2 ns
(2) The HS_IN, VS_IN, and FID input setup/hold times are valid for 3.3-V I/O operation only. These sync inputs are not recommended for
use with 1.8-V I/O logic levels.
(3) Defined as the delay on Y pixel data, starting from the rising edge of CLKIN, until the clock period.
(4) CSC contribution: 8 pixels, CSM contribution: 1 pixel, 2x interpolation filter contribution: 18 pixels
(5) PSRR is defined as 20*log (ripple voltage at DAC output/ripple voltage at AVDD input). Limits from characterization only.
(6) Crosstalk spec applies to each possible pair of the 3 DAC outputs. Limit from characterization only.
(7) The imbalance between DACs applies to all possible pairs of the three DACs.
(8) Nominal values at R_FS = R_FS(nom), see Figure 7-12 . Limit from characterization only. Excludes bias offset.
90
Electrical Characteristics
Submit Documentation Feedback
Product Folder Link(s): THS8200-EP
Copyright © 2009, Texas Instruments Incorporated