THS8200-EP Datasheet, PDF (70/104 Pages) Texas Instruments – All-Format Oversampled Component Video/PC Graphics D/A System With Three 11-Bit DACs, CGMS Data Insertion

THS8200-EP
SLES253 – DECEMBER 2009
www.ti.com
csc_bfc3(9:0):
B/Cb input channel – R/Cr output channel, fractional part
{csc_b31 0x14(1:0) and [00 0000 0000]
csc_b32 0x15(7:0)}
10-bit fractional portion of coefficient that is multiplied with B/Cb input, to produce R/Cr output
(magnitude format)
csc_offset1(9:0):
DAC channel 1 offset
{csc_offs1 0x16(7:0)
and
csc_offs12 0x17(7:6)}
[00 0000 0000]
Offset value for G/Y output (signed magnitude format)
csc_offset2(9:0):
DAC channel 2 offset
{csc_offs12 0x17(5:0)
and
csc_offs23 0x18(7:4)}
[00 0000 0000]
Offset value for B/Cb output (signed magnitude format)
csc_offset3(9:0):
DAC channel 3 offset
{csc_offs23 0x18(3:0)
and
csc_offs3 0x19(7:2)}
[00 0000 0000]
Offset value for R/Cr output (signed magnitude format)
csc_bypass:
Bypass for CSC block
{csc_offs3 0x19(1)}
[1]
0 : Color space conversion (CSC) not bypassed
1 : CSC bypassed
csc_uof_cntl:
Under-/overflow control for CSC block
{csc_offs3 0x19(1)}
[0]
Controls over-/underflow protection logic on color space converter
0 : Under-/overflow protection off
1 : Under-/overflow protection on
5.1.3 Test Control (Sub-Addresses 0x1A−0x1B)
tst_digbypass:
Bypass to DAC inputs
{tst_cntl1 0x1A(7)}
[0]
0 : Normal operation; nonbypass
1 : Digital logic bypassed to directly control DACs from input bus
tst_offset:
Bypass for DAC offsets
{tst_cntl1 0x1A(6)}
[0]
0 : Normal operation; logic not bypassed
1 : Programmed offsets are always added to DAC codes regardless of mode or dtg_state
tst_ydelay(1:0):
Y delay path control
70
I²C Register Map
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