THS8200-EP Datasheet, PDF (55/104 Pages) Texas Instruments – All-Format Oversampled Component Video/PC Graphics D/A System With Three 11-Bit DACs, CGMS Data Insertion

THS8200-EP
www.ti.com
SLES253 – DECEMBER 2009
Figure 4-40 shows the linear DAC I/O relationship for either of the two nominal full-scale settings.
Ramping Output With Different Full-Scale Ranges
1.305 V
0.700 V
0
255
511
767
1023
Input Digital Codes
Figure 4-40. Ramping Output With Different Full-Scale Ranges
4.8.2 SMPTE-Compatible RGB Output With Sync Signal Inserted on G (Green) Channel
In this mode, a tri-level (HDTV modes)/bi-level (SDTV modes) sync signal is inserted into the G channel.
The nominal analog output voltage range, which is from the sync tip to the peak of active video, is from
0.0 V to 1.050 V. During the active video period, the peak-to-peak ac value (dynamic range) is 700 mV
(from 350 mV to 1050 mV). The blank levels on all three channels correspond to the bottom code 64 and
are at 350 mV. Figure 4-41 and Figure 4-42 illustrate the analog video output signals, both the output from
the G channel with a tri-level or a bi-level sync pulse inserted, as well as the outputs from R and B
channels. No sync signal is inserted during the sync period on R and B channels.
Alternatively, sync can be inserted on all three channels on THS8200 by appropriately programming the
sync amplitude levels. On those channels where no sync is inserted, the blank levels are maintained at a
350-mV dc level.
The range of active video codes on the R, G, and B channels is from 64 to 940. By definition, code 64
corresponds to blank-level output, and code 940 corresponds to peak analog output. Input codes outside
this region can either be clipped by THS8200 or can be passed, depending on the CSM setting. When
passed, the user should make sure not to overdrive the DAC outputs outside the DAC output compliance
range if instantaneously high output codes would occur.
Copyright © 2009, Texas Instruments Incorporated
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Detailed Functional Description
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