THS8200-EP Datasheet, PDF (60/104 Pages) Texas Instruments – All-Format Oversampled Component Video/PC Graphics D/A System With Three 11-Bit DACs, CGMS Data Insertion

THS8200-EP
SLES253 – DECEMBER 2009
www.ti.com
CGMS is inserted on line 41 as prescribed by EIA 770 standards for progressive format display of SDTV.
Fourteen bits can be inserted on this line, consisting of 6 bits header and 8 bits payload. The user can
directly program these bits into the corresponding THS8200 registers. Care should be taken to format this
data according to CGMS semantics; the user is referred to the original standards to determine
header/payload data programming. To avoid the transmission of invalid data, the data transmitted is
updated only when the CGMS register with the highest subaddress is programmed with cgms_en active.
CGMS insertion is possible in either 1× or 2× interpolated video modes of the THS8200. While EIA-805
allows the inserted data to change on every frame, and also allows data packets that would span multiple
lines (and therefore also multiple frames, since only 1 line/frame is used for insertion), the THS8200 does
not support multiline data insertion because it is not required for CGMS.
4.12 I²C Interface
The THS8200 contains a slave-only I²C interface on which both write and read are supported. The register
map shows which registers support read/write (R/W) and which are read-only (R). The device supports
normal and fast I²C modes (SCL up to 400 kHz). The I²C interface is also operational when no input clock
is received on CLKIN.
To discriminate between write and read operations, the device is addressed at separate device addresses.
There is an automatic internal sub-address increment counter to efficiently write/read multiple bytes in the
register map during one write/read operation. Furthermore, bit1 of the I²C device address is dependent
upon the setting of the I2CA pin, as follows:
• If address-selecting pin I2CA = 0, then
– write address is 40h (0100 0000)
– read address is 41h (0100 0001)
• If address-selecting pin I2CA = 1, then
– write address is 42h (0100 0010)
– read address is 43h (0100 0011)
The I²C interface supports fast I²C, i.e., SCL up to 400 kHz.
WRITE FORMAT
S
Slave address(w)
A
Sub-address
A
Data0
A
S
Slave address(w)
A
Sub-address
Data0
DataN-1
P
Start condition
0100 0000 (0x40) if I2CA = 0, or 0100 0010 (0x42) if I2CA = 1
Acknowledge, generated by the THS8200
Sub-address of the first register to write, length: 1 byte
First byte of the data
Nth byte of the data
Stop condition
......
DataN- A
P
1
READ FORMAT
First write the sub-address, where the data must be read out to the THS8200 in the format as follows:
S
Slave address(w)
A
Sub-address
A
P
S
Slave address(r)
A
DataN
AM Data(N+1) AM
......
NAM
P
S
Start condition
Slave address(r)
0100 0001 (0x41) if I2CA = 0, or 0100 0011 (0x43) if I2CA = 1
A
Acknowledge, generated by the THS8200; if the transmission is successful, then A = 0, else A = 1
AM
Acknowledge, generated by a master
NAM
Not acknowledge, generated by a master
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Detailed Functional Description
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