THS8200-EP Datasheet, PDF (81/104 Pages) Texas Instruments – All-Format Oversampled Component Video/PC Graphics D/A System With Three 11-Bit DACs, CGMS Data Insertion

THS8200-EP
www.ti.com
SLES253 – DECEMBER 2009
dtg2_line_cnt(10:0):
Line count readback
{dtg2_lined_cnt_msb 0x7F(2:0) and dtg2_line_cnt_lsb 0x80(7:0)}
Reports the number of Hsync input pulses between consecutive dtg_start signals (i.e., over one
frame period)
dtg2_fid_de_cntl:
FID (field-ID)/DE (data enable)input selection for FID
terminal
{dtg2_cntl 0x82(7)}
[0]
Controls interpretation of signal on FID terminal
0 : Signal interpeted as FieldID
1 : If the DTG is programmed to the VESA mode, the FID pin becomes a data-enable input pin. Data
enable is assumed high during the active video window, and low outside this area. This is
compatible with the DE signal from TI DVI receivers. Data is passed through the THS8200 only
when data enable is high. Otherwise, the input data is overridden by the THS8200 internally
programmed blanking value. If the DTG is programmed in the SDTV or HDTV video mode with
dedicated timing signals, a 1 in this register location causes the THS8200 to generate an internal
FieldID value from the relative alignment of Hsync and Vsync inputs, rather than using the signal on
the FID input pin (which is ignored). This is for EIA-861 compliant operation for video-over-DVI 1.0
(with HDCP) where there is no dedicated FID signal available but the even/odd field ID is determined
from Hsync/Vsync alignment.
dtg2_rgb_mode_on:
RGB/YPbPr mode selection
{dtg2_cntl 0x82(6)}
[1]
This selection affects the relative blank vs video level position: on R,G,B, and Y channels an offset is
added to the DAC outputs
0 : YPbPr mode (blanking at bottom range for Y – mid-range for Pb, Pr channels)
1 : RGB mode (blanking at bottom ranges for all channels)
dtg2_embedded_timing:
Video sync input source
{dtg2_cntl 0x82(5)}
[0]
0 : Timing of video input bus is derived from HS, VS, and FID dedicated inputs
1 : Timing of video input bus is assumed embedded in video data using SAV/EAV code sequences.
dtg2_vsout_pol:
{dtg2_cntl 0x82(4)}
0 : Positive polarity
1 : Negative polarity
VS_OUT polarity
[1]
dtg2_hsout_pol:
{dtg2_cntl 0x82(3)}
0 : Negative polarity
1 : Positive polarity
HS_OUT polarity
[1]
dtg2_fid_pol:
{dtg2_cntl 0x82(2)}
0 : Negative polarity
1 : Positive polarity
FID polarity
[1]
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I²C Register Map
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