THS8200-EP Datasheet, PDF (24/104 Pages) Texas Instruments – All-Format Oversampled Component Video/PC Graphics D/A System With Three 11-Bit DACs, CGMS Data Insertion

THS8200-EP
SLES253 – DECEMBER 2009
www.ti.com
4.4 Color Space Conversion (CSC)
THS8200 contains a fully-programmable 3×3 multiply/add and 3×1 adder block that can be switched in for
all video formats up to a pixel clock frequency of 150 MHz. Color space conversion is thus available for all
DTV modes, including 1080P and VESA modes up to SXGA at 75 Hz (135 MSPS). The operation is done
after optional 4:2:2 to 4:4:4 conversion, and thus on the 1× pixel clock video data prior to optional 2× video
oversampling. The CSC block can be switched in or bypassed depending on the setting of register
csc_bypass.
Each of the nine floating point multiplier coefficients of the 3×3 multiply/add is represented as the
combination of a 6-bit signed binary integer part, and a 10-bit fractional part. The integer part is a signed
magnitude representation with the MSB as the sign bit. The fractional part is a magnitude representation;
see the following example.
The register nomenclature is: csc_<r,g,b> <i,f>c<1,2,3> where:
• <r,g,b> identifies which input channel is multiplied by this coefficient (r = red/Cr, g = green/Y,
b = blue/Cb input).
• <i,f> identifies the integer (i) or fractional (f) part of the coefficient.
• <1,2,3> identifies the output channel from the color space converter: 1 = Yd/Gd, 2 = Cb/Bd, 3 = Cr/Rd.
For the offset values, a value of 1/4 of the desired digital offset needs to be programmed in the individual
offset register, so a typical offset of 512 (offset over 1/2 of the video range) requires programming a value
of 128 decimal into the offset<1,2,3> registers, where again <1,2,3> defines the output channel affected,
with similar convention as shown previously.
Saturation logic can be switched in to avoid over- and underflow on the result after color space conversion
using the csc_uof_cntl register.
We next show an example of how to program the CSC. This also explains the numeric data formats.
CSC configuration example: HDTV RGB to HDTV YCbCr
The formulas for RGB to YCbCr conversion are:
• Yd = 0.2126*Rd + 0.7152*Gd + 0.0722*Bd
• Cb = −0.1172*Rd – 0.3942*Gd + 0.5114*Bd + 512
• Cr = 0.5114*Rd – 0.4646*Gd – 0.0468*Bd + 512
To program the red coefficient of channel 1 (Y) with the value of 0.2126 the following must be done:
1. Realize that this is a positive value so the sign bit of the integer part is 0 (bit 5 of csc_ric1 = 0).
2. Note that there is no integer portion of the coefficient (bit 4−bit 0 = 00000).
3. The binary representation of the fractional part can be constructed directly from the binary equivalent
of the fractional part multiplied by 1024 (0.2126 × 1024 = 217.7), rounded to the nearest integer (218)
and represented as a binary 10-bit number (00 1101 1010).
Using the above method all the registers for the CSC blocks can be programmed with the correct value for
RGB to YCbCr conversion. Below is a complete list of register values for the above conversion.
0.2126 → csc_ric1 = 00 0000
0.7152 → csc_gic1 = 00 0000
0.0722 → csc_bic1 = 00 0000
−0.1172 → csc_ric2 = 10 0000
−0.3942 → csc_gic2 = 10 0000
0.5114 → csc_bic2 = 00 0000
0.5114 → csc_ric3 = 00 0000
−0.4646 → csc_gic3 = 10 0000
−0.0468 → csc_bic3 = 10 0000
csc_rfc1 = 00 1101 1010
csc_gfc1 = 10 1101 1100
csc_bfc1 = 00 0100 1010
csc_rfc2 = 00 0111 1000
csc_gfc2 = 01 1001 0100
csc_bfc2 = 10 0000 1100
csc_rfc3 = 10 0000 1100
csc_gfc3 = 01 1101 1100
csc_bfc3 = 00 0011 0000
24
Detailed Functional Description
Submit Documentation Feedback
Product Folder Link(s): THS8200-EP
Copyright © 2009, Texas Instruments Incorporated