THS8200-EP Datasheet, PDF (25/104 Pages) Texas Instruments – All-Format Oversampled Component Video/PC Graphics D/A System With Three 11-Bit DACs, CGMS Data Insertion

THS8200-EP
www.ti.com
SLES253 – DECEMBER 2009
For the offsets necessary in the second and third equation the csc_offset<n> registers need to be
programmed. We need to add 512 to the Cb and Cr channels. The value to be programmed is 1/4 of this
offset in a signed magnitude representation, thus 128 or csc_offset2 = csc_offset3 = 00 1000 0000.
Packing these individual registers into the I²C register map, the programmed values are:
SUBADDRESS
REGISTER NAME
VALUE
0x04
csc_r11
0000 0000
0x05
csc_r12
1101 1010
0x06
csc_r21
1000 0000
0x07
csc_r22
0111 1000
0x08
csc_r31
0000 0010
0x09
csc_r32
0000 1100
0x0A
csc_g11
0000 0010
0x0B
csc_g12
1101 1100
0x0C
csc_g21
1000 0001
0x0D
csc_g22
1001 0100
0x0E
csc_g31
1000 0001
0x0F
csc_g32
1101 1100
0x10
csc_b11
0000 0000
0x11
csc_b12
0100 1010
0x12
csc_b21
0000 0010
0x13
csc_b22
0000 1100
0x14
csc_b31
1000 0000
0x15
csc_b32
0011 0000
0x16
csc_offs1
0000 0000
0x17
csc_offs12
0000 1000
0x18
csc_offs23
0000 0010
0x19
csc_offs3
0000 0000
CSC configuration example: HDTV YCbCr to HDTV RGB
• Gd = –0.4577*Cr + Yd – 0.1831*Cb +328 (= 0.6408*128*4)
• Bd = 0*Cr + Yd + 1.8142* Cb – 929 (= −1.8142*128*4)
• Rd = 1.5396* Cr +Yd +0*Cb – 788 (= −1.5396*128*4)
Copyright © 2009, Texas Instruments Incorporated
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Detailed Functional Description
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