THS8200-EP Datasheet, PDF (59/104 Pages) Texas Instruments – All-Format Oversampled Component Video/PC Graphics D/A System With Three 11-Bit DACs, CGMS Data Insertion

THS8200-EP
www.ti.com
4.8.6 Summary of Supported Video Formats
Range of input
codes
Peak level
Blank level
DC level shift
during active
video period
RGB WITHOUT
SYNC
0 to 1023
700 mV or 1305 mV
0V
RGB SYNC ON G
64 to 940
1050 mV
350 mV
0
350 mV
RGB SYNC
ON ALL
64 to 940
1050 mV
350 mV
350 mV
SLES253 – DECEMBER 2009
YPbPr SYNC ON Y YPbPr SYNC ON ALL
64 to 940 on Y;
64 to 960 on Cr and Cb
1050 mV
350 mV
64 to 940 on Y;
64 to 960 on Cr and Cb
1050 mV
350 mV
350 mV
350 mV
4.9 Test Functions
The user can activate a 75% SMPTE color bar test pattern when the device is configured in VESA mode
using the vesa_colorbars register setting. The width of each color bar can be programmed using the
dtg1_vesa_cbar_size register.
The digital logic in front of the DACs can be completely bypassed and the DACs can be driven directly
with levels programmed from the I²C interface by activating the dac_i2c_cntl register. In this case the
dac<n>_cntl registers set the DAC input codes. A fast or slow ramp signal can be internally generated and
sent to the DACs using tst_fastramp and tst_slowramp registers. This could be useful for a static DAC
linearity test.
Alternatively, the input bus can directly drive the DACs when the tst_digbypass register is activated for
tests at full speed.
The delay of the Y channel can be changed in YCbCr modes with respect to Cb and Cr channels by
programming the tst_ydelay register.
Finally, there is a digital output port with data encoded according to ITU-R.BT656. This is a loop-through
of the original input bus, prior to any THS8200 internal processing, and thus only provides standard data
when input to the THS8200 is provided in a 10-bit ITU-R BT.656 format. This output bus could be used to
connect to a separate NTSC/PAL video encoder. The data_clk656_on register activates the clock output
on this bus and the data_tristate656 register disables the output bus. It is recommended to disable this
output when not in use.
4.10 Power Down
THS8200 implements two power-down modes: dac_pwdn powers down the DAC channels but keeps all
digital logic active; chip_pwdn powers down the digital logic except the I²C interface. Activating both
registers enforces a complete analog/digital power down except for the I²C interface.
4.11 CGMS Insertion
The THS8200 can embed data within the vertical blanking interval, encoded according to the EIA-805 data
insertion standard. CGMS is an implementation of the EIA-805 standard that defines data insertion in
component video interface (CVI) video signals.
The THS8200 supports CGMS data insertion on line 41 of every frame in the 525P format. The data is
inserted on the Y channel only; Pb and Pr channels remain at the blanking level. CGMS data insertion is
enabled by activating the cgms_en register and programming the cgms_header and cgms_payload
registers appropriately. The user needs to program header and payload data in the correct format, as no
additional data encoding is done prior to insertion into the analog DAC output. The THS8200 only
performs a play-out function for the programmed data. The CGMS encoding block assumes that a full
10-bit video range is used in order to determine the 70% of peak-white amplitude of a logic 1 bit, as
prescribed by EIA-805. The CSM does not affect the amplitude of the CGMS data insertion.
Copyright © 2009, Texas Instruments Incorporated
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Detailed Functional Description
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