THS8200-EP Datasheet, PDF (58/104 Pages) Texas Instruments – All-Format Oversampled Component Video/PC Graphics D/A System With Three 11-Bit DACs, CGMS Data Insertion

THS8200-EP
SLES253 – DECEMBER 2009
Analog Output of Cr and Cb Channels Without Sync Insertion
E’cr, E’cb
700 mV
960
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350 mV
0 mV
Active Video Period
512
Blank Level
64
Blanking Interval
Figure 4-45. Analog Output of Cr and Cb Channels Without Sync Insertion
The blanking level of all channels is at 350 mV. Note that for the Pb and Pr output channels, there is no dc
offset added, so DAC input code 0 now corresponds to 0 V dc output. Whether or not offset is added to
the DAC outputs is determined from the setting of the dtg2_rgb_mode_on register.
4.8.5 SMPTE-Compatible YPbPr Output With Sync Signal Inserted on All Channels
In this mode, sync signals are inserted on all three channels Y, Cr, and Cb. The Y channel output is
identical to that of Section 4.8.4. The Pb and Pr channel outputs are shown below. The range of input
codes to the Y channel is from 64 to 940. The range of input codes to the CrCb channels is from 64 to
960.
Analog Output of Cr and Cb Channels With Sync Insertion
E’cr, E’cb
700 mV
960
650 mV
896
350 mV
50 mV
0 mV
Active Video Period
512
Blank Level
128
64
Blanking Interval
OH
Figure 4-46. Analog Output of Cr and Cb Channels With Sync Insertion
The ac dynamic range during the active video period is the same on all channels, 700 mV. This means
that two different code ranges are mapped to the same analog output range. Because three DACs in the
THS8200 share a common full-scale adjust resistor, therefore, different input codes to the DAC result in
different analog outputs. In order to map two code ranges into a same analog output, the input code range
must be scaled in the CSM block.
58
Detailed Functional Description
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