THS8200-EP Datasheet, PDF (33/104 Pages) Texas Instruments – All-Format Oversampled Component Video/PC Graphics D/A System With Three 11-Bit DACs, CGMS Data Insertion

THS8200-EP
www.ti.com
SLES253 – DECEMBER 2009
4.7 Display Timing Generator (DTG)
4.7.1 Overview of Functionality
THS8200 can generate dedicated Hsync/Vsync/FieldID video synchronization outputs, as well as a
composite sync inserted on either the G/Y or all analog output channels. Both types of output
synchronization can be available simultaneously and programmed independently. Synchronization
patterns are fully programmable to accommodate all standard VESA (PC graphics) and ATSC (DTV)
formats as well as nonstandard formats.
For the purpose of output video timing generation, the device is configured in HDTV, SDTV or VESA
mode (dtg1_mode register). Depending on the selected DTG mode, a number of line types are available
to generate the full video frame format. The timing and position of horizontal and vertical syncs, the
position of horizontal and vertical blanking intervals, and the structure, position and width of equalization
pulses, pre- and post-serration pulses within the vertical blanking interval are user-programmable.
The DTG determines:
• the frame format/field format (number of pixels/line, number of lines/field1, number of lines/field2,
number of fields/frame = 1 for progressive or 2 for interlaced formats) and its synchronization to the
input data source.
– Registers: dtg1_total_pixels, dtg1_linecnt, dtg1_frame_size, dtg1_field_size
• in slave mode, whether HS_IN, VS_IN, FID (dedicated sync inputs) are used for input video
synchronization or video timing is extracted from embedded SAV/EAV codes, as well as the relative
position of the video frame with respect to these synchronization signals.
– Registers: dtg2_embedded_timing, dtg2_hs_in_dly, dtg2_vs_in_dly
• the I/O direction of the HS_IN and VS_IN input signals (master vs slave mode), and the polarity of the
HS_IN, VS_IN, and FID signals.
– Registers: dtg2_hs_pol, dtg2_vs_pol, dtg2_fid_pol
• the position and width of the HS_OUT, VS_OUT output signals, and their polarity.
– Registers: dtg2_hlength, dtg2_hdly, dtg2_vlength1, dtg2_vdly1, dtg2_vlength2, dtg2_vdly2,
dtg2_vsout_pol, dtg2_hsout_pol
• field reversal within DTG.
– Register: dtg1_field_flip
• the active video window: width and position of horizontal blanking interval, width and position of vertical
blanking interval.
– Registers: dtg2_bp<n>, dtg2_linetype<n> and the dtg1_spec_x registers, see DTG Line Type
Overview (Section 4.7.3).
• the composite sync format: horizontal line timing includes serration, interlaced sync and broad pulses
on each line in vertical blanking interval, width of vertical sync.
– Registers: dtg1_mode, dtg1_spec_<a,b,c,d,d1,e,g,h,i,k,k1>
• the behavior of the composite sync insertion: inserted on G/Y-channel only, or inserted on all channels,
or no composite sync insertion; the amplitudes of the inserted negative and positive sync, the
amplitudes of all serration pulses and broad pulses during the vertical blanking interval.
– Registers: dtg1_<y,cbcr>_sync_high, dtg1_<y,cbcr>_sync_low
• the DAC output amplitude during blanking and whether video data is passed or not during the active
video portion of lines within the vertical blanking interval that contain no vertical sync, serration, or
broad pulses.
– Registers: dtg1_<y,cbcr>_blank, dtg1_pass_through
• the width of each color bar of the color bar test pattern.
– Registers: dtg1_vesa_cbar_size
Copyright © 2009, Texas Instruments Incorporated
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Detailed Functional Description
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