LP3918 Datasheet, PDF (6/39 Pages) National Semiconductor (TI) – Battery Charge Management and Regulator Unit

LP3918
SNVS476D – AUGUST 2007 – REVISED MAY 2013
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Thermal Properties ⁽¹⁾
Junction to Ambient Thermal Resistance θ_JA
Jedec Standard Thermal PCB
4L Cellphone Board
37°C/W
66°C/W
(1) Junction-to-ambient thermal resistance (θ_JA) is taken from thermal modelling result, performed under the conditions and guidelines set
forth in the JEDEC standard JESD51-7. The value of (θ_JA) of this product could fall within a wide range, depending on PWB material,
layout, and environmental conditions. In applications where high maximum power dissipation exists (high V_IN, high I_OUT), special care
must be paid to thermal dissipation issues in board design.
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