LP3918 Datasheet, PDF (28/39 Pages) National Semiconductor (TI) – Battery Charge Management and Regulator Unit

LP3918
SNVS476D – AUGUST 2007 – REVISED MAY 2013
No-Load Stability
The LDO's on the LP3918 will remain stable in regulation with no external load.
www.ti.com
Table 19. LDO Output Capacitors Recommended Specification
Symbol
Parameter
Capacitor Type
Typ
C_o(LDO1)
Capacitance
X5R. X74
1.0
C_o(LDO2)
Capacitance
X5R. X74
1.0
C_o(LDO3)
Capacitance
X5R. X74
1.0
C_o(LDO4)
Capacitance
X5R. X74
1.0
C_o(LDO5)
Capacitance
X5R. X74
1.0
C_o(LDO6)
Capacitance
X5R. X74
1.0
C_o(LDO7)
Capacitance
X5R. X74
1.0
Limit
Min
Max
0.7
2.2
0.7
2.2
0.7
2.2
0.7
2.2
0.7
2.2
0.7
2.2
0.7
2.2
Units
µF
µF
µF
µF
µF
µF
µF
Note: The capacitor tolerance should be 30% or better over the full temperature range. X7R or X5R capacitors
should be used. These specifications are given to ensure that the capacitance remains within these values over
all conditions within the application. See Capacitor Characteristics.
Thermal Shutdown
The LP3918 has internal limiting for high on-chip temperatures caused by high power dissipation etc. This
Thermal Shutdown, TSD, function monitors the temperature with respect to a threshold and results in a device
power-down.
If the threshold of +160°C has been exceeded then the device will power down. Recovery from this TSD event
can only be initiated after the chip has cooled below +115°C. This device recovery is controlled by the
APU_TSD_EN bit (bit 1) in control register MISC, 8h'1C. See Table 21 If the APU_TSD_EN is set low then the
device will shutdown requiring a new start up event initiated by PWR_ON, HF_PWR, or CHG_IN. If
APU_TSD_EN is set high then the device will power up automatically when the shutdown condition clears. In this
case the control register settings are preserved for the device restart.
The threshold temperature for the device to clear this TSD event is 115°C. This threshold applies for any start up
thus the device temperature must be below this threshold to allow a start up event to initiate power up.
Further Register Information
STATUS REGISTER READ ONLY
BIT
7
6
5
(1) Bits <4..0> are not used.
Table 20. Register Address 8h'0C: Status⁽¹⁾
NAME
PWR_ON
_TRIG
HF_PWR
_TRIG
CHG_IN
_TRIG
FUNCTION (if bit = '1')
PMU start up is initiated by PWR_ON.
PMU start up is initiated by HF_PWR.
PMU start up is initiated by CHG_IN.
MISC CONTROL REGISTER
Table 21. Register Address 8h'1C: Misc⁽¹⁾
BIT
NAME
FUNCTION (if bit = '1')
1
APU_TSD
1b' 0: Device will shutdown completely if thermal shutdown occurs.
_EN
Requires a new start up event to restart the PMU.
1b'1: Device will start up automatically after thermal shutdown
condition is removed. (Device tries to keep its internal state.)
(1) Bits <7..2> are not used.
28
Submit Documentation Feedback
Product Folder Links: LP3918
Copyright © 2007–2013, Texas Instruments Incorporated