LP3918 Datasheet, PDF (18/39 Pages) National Semiconductor (TI) – Battery Charge Management and Regulator Unit

LP3918
SNVS476D – AUGUST 2007 – REVISED MAY 2013
Figure 5. Device Power Up Logic Timing. CHG_IN, HF_PWR
320 ms
If charger is connected (CHG_IN) or HF_PWR is
applied, then both events are filtered for 320 ms
before enabling LDO1
CHG_IN
HF_PWR
PS_HOLD needs to be asserted within 1200 ms after
CHG_IN or HF_PWR rising edge has been detected.
(HF_PWR level detected for LP3918TL-C)
1.2s
Debounce time before normal start up sequence, 320 ms.
PS_HOLD
PS_HOLD high < 1.2s from I/P detection
LDO1
LDO2
RESET
LDO3
LDO7
RX_EN, TX_EN,
TCXO_EN
LDO4,5,6
87% Reg
< 200 Ps
87% Reg
60 ms
I2C Control
Note: Serial I/F commands only take place
after PS_HOLD is asserted.
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