LP3918 Datasheet, PDF (2/39 Pages) National Semiconductor (TI) – Battery Charge Management and Regulator Unit

LP3918
SNVS476D – AUGUST 2007 – REVISED MAY 2013
Device Pin Diagram
Figure 2. LP3918 25 pin DSBGA Package
TOP VIEW
5
ACOK
_N
LDO7
LDO6
LDO5
VIN2
4
RESET
_N
PON
_N
TX_EN
RX_EN
LDO4
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3
VSS
SCL
SDA
GNDA
LDO3
2
PS_
HOLD
PWR
_ON
HF
PWR
TCXO
_EN
LDO2
1
IMON
CHGIN
BATT
VIN1
LDO1
A
B
C
D
E
TOP VIEW
Pin #
A1
A2
A3
A4
A5
B1
B2
B3
B4
B5
C1
C2
C3
C4
C5
D1
D2
D3
D4
D5
Name
IMON
PS_HOLD
VSS
RESET_N
ACOK_N
CHG_IN
PWR_ON
SCL
PON_N
LDO7
BATT
HF_PWR
SDA
TX_EN
LDO6
VIN1
TCXO_EN
GNDA
RX_EN
LDO5
PIN DESCRIPTION
Type ⁽¹⁾
Description
A
Charge current monitor output. This pin presents an analog
voltage representation of the input charging current. VIMON(mV) =
(2.47 x ICHG)(mA).
DI
Input for power control from external processor/controller.
G
Digital Ground pin
DO
Reset Output. Pin stays LOW during power up sequence. 60ms
after LDO1 (CORE) is stable this pin is asserted HIGH.
DO
AC Adapter indicator, LOW when 4.5V – 6.0V present at CHG_IN.
P
DC power input to charger block from wall or car power adapters.
DI
Power up sequence starts when this pin is set HIGH. Internal
500kΩ pull-down resistor.
DI
Serial Interface Clock input. External pull up resistor is needed, typ
1.5kΩ
DO
Active low signal is PWR_ON inverted
A
LDO7 Output (GP)
P
Main battery connection. Used as a power connection for current
delivery to the battery.
DI
Power up sequence starts when this pin is set HIGH. Internal
500kΩ pull-down resistor.
DI/O
Serial Interface, Data Input/Output Open Drain output, external pull
up resistor is needed, typ 1.5kΩ.
DI
Enable control for LDO6 (TX). HIGH = Enable, LOW = Disable.
A
LDO6 Output (TX)
P
Battery Input for LDO1 - 2
DI
Enable control for LDO4 (TCXO). HIGH = Enable, LOW = Disable.
G
Analog Ground pin
DI
Enable control for LDO5 (RX). HIGH = Enable, LOW = Disable.
A
LDO5 Output (RX)
(1) A: Analog. D: Digital. I: Input. DI/O: Digital Input/Output. G: Ground. O: Output. P: Power.
2
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