LP3918 Datasheet, PDF (11/39 Pages) National Semiconductor (TI) – Battery Charge Management and Regulator Unit

LP3918
www.ti.com
SNVS476D – AUGUST 2007 – REVISED MAY 2013
Charger Electrical Characteristics
Unless otherwise noted, V_CHG-IN = 5V, V_IN ( = VIN1 = VIN2 = BATT) = 3.6V.C_{CHG_IN} = 10µF, C_BATT = 30µF. Charger set to
default settings unless otherwise noted. Typical values and limits appearing in normal type apply for T_J = 25°C. Limits
appearing in boldface type apply over the entire junction temperature range for operation, T_a = T_J = −25°C to +85°C. ⁽¹⁾⁽²⁾
Symbol
Parameter
Condition
Limit
Typ
Units
Min
Max
V_CHG-IN
Input Voltage
Range
Operating Range
4.5
6.5
V
4.5
6
V_{OK_CHG}
CHG_IN OK trip- V_{CHG_IN} - V_BATT (Rising)
200
mV
point
V_{CHG_IN} - V_BATT (Falling)
50
V_TERM
Battery Charge
Termination
voltage
Default
4.2
V
I_CHG
V_TERM voltage
tolerance
Fast Charge
Current Accuracy
T_J = 25°C
T_J = 0°C to 85°C
I_CHG = 450mA
-0.35
+0.35
%
-1
+1
-10
+10
%
Programmable full-
rate charge current
range(default
100mA)
6.0V ≥ V_{CHG_IN} ≥ 4.5V
V_BATT < (V_{CHG_IN} - V_{OK_CHG})
V_{FULL_RATE} < V_BATT < V_TERM
(3)
50
950
mA
Default
100
Charge current
50
programming step
I_PREQUAL
Pre-qualification
current
V_BATT = 2V
50
40
60
mA
I_{CHG_USB}
CHG_IN
5.5V ≥ V_{CHG_IN} ≥
Low
programmable
4.5V
current in USB
mode
V_BATT < (V_{CHG_IN} -
V_{OK_CHG})
100
mA
V_{FULL_RATE} < V_BATT High
< V_TERM
450
Default = 100mA
100
V_{FULL_RATE}
Full-rate
V_BATT rising, transition from pre-qual to
3.0
2.9
3.1
qualification
full-rate charging
V
threshold
I_EOC
End of Charge
0.1C option selected
10
Current, % of full-
%
rate current
V_RESTART
Restart threshold V_BATT falling, transition from EOC to full-
4.05
3.97
4.13
voltage
rate charge mode. Default options
V
selected - 4.05V
I_MON
T_REG
I_MON Voltage 1
I_MON Voltage 2
Regulated junction
temperature
I_CHG = 100mA
I_CHG = 450mA
(4)
0.247
V
1.112
0.947
1.277
115
°C
(1) All electrical characteristics having room-temperature limits are tested during production with T_J = 25°C. All hot and cold limits are
specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control.
(2) Junction-to-ambient thermal resistance (θ_JA) is taken from thermal modelling result, performed under the conditions and guidelines set
forth in the JEDEC standard JESD51-7. The value of (θ_JA) of this product could fall within a wide range, depending on PWB material,
layout, and environmental conditions. In applications where high maximum power dissipation exists (high V_IN, high I_OUT), special care
must be paid to thermal dissipation issues in board design.
(3) Full charge current is specified for CHG_IN = 4.5 to 6.0V. At higher input voltages, increased power dissipation may cause the thermal
regulation to limit the current to a safe level, resulting in longer charging time.
(4) Specified by design. Not production tested.
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