LP3918 Datasheet, PDF (32/39 Pages) National Semiconductor (TI) – Battery Charge Management and Regulator Unit

LP3918
SNVS476D – AUGUST 2007 – REVISED MAY 2013
Slave Address
Control Register Add.
Slave Address
S
(7 bits)
'0' A
(8 bits)
A Sr
(7 bits)
'1' A
Register Data
(8 bits)
A/
NA
P
R/W
From Slave to Master
From Master to Slave
R/W
Data transferred, byte +
Ack/NAck
Direction of the transfer
will change at this point
A - ACKNOWLEDGE (SDA Low)
NA - ACKNOWLEDGE (SDA High)
S - START CONDITION
Sr - REPEATED START CONDITION
P - STOP CONDITION
Figure 18. Register Read Format
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