LP3918 Datasheet, PDF (14/39 Pages) National Semiconductor (TI) – Battery Charge Management and Regulator Unit

LP3918
SNVS476D – AUGUST 2007 – REVISED MAY 2013
www.ti.com
REGISTER INFORMATION, SLAVE ADDRESS CODE 7H’7E
Table 3. Control Registers⁽¹⁾⁽²⁾
Addr
8h'00
8h'01
8h'02
8h'03
8h'04
8h'05
8h'06
8h'07
8h'0C
8h'10
8h'11
8h'12
8h'13
8h'14
8h'1C
Register
(default
value)
OP_EN
(0000 0101)
LDO1PGM
O/P
(0000 0001)
LDO2PGM
O/P
(0000 1011)
LDO3PGM
O/P
(0000 1011)
LDO4PGM
O/P
(0000 1011)
LDO5PGM
O/P
(0000 1011)
LDO6PGM
O/P
(0000 1011)
LDO7PGM
O/P
(0000 1011)
STATUS
(0000 0000)
CHGCNTL1
(0000 1001)
CHGCNTL2
(0000 0001)
CHGCNTL3
(0001 0010)
CHGSTATU
S1
CHGSTATU
S2
MISC
Control1
D7
X
X
X
X
X
X
X
X
PWR_ON
_TRIG
USBMODE
_EN
Batt_Over
_Out
D6
X
X
X
X
X
X
X
X
HF_PWR
_TRIG
CHGMODE
_EN
CHGIN_
OK_Out
D5
X
X
X
X
X
X
X
X
CHG_IN
_TRIG
Force EOC
VTERM[1]
EOC
D4
X
X
X
X
X
X
X
X
X
TOUT_
doubling
Prog_
ICHG[4]
VTERM[0]
Tout_
Fullrate
D3
LDO7_EN
V1_OP[3]
V2_OP[3]
V3_OP[3]
V4_OP[3]
V5_OP[3]
V6_OP[3]
V7_OP[3]
X
EN_Tout
Prog_
ICHG[3]
Prog_
EOC[1]
Tout_
Prechg
D2
D1
D0
LDO3_EN
X
LDO1_EN
V1_OP[2] V1_OP[1] V1_OP[0]
V2_OP[2] V2_OP[1] V2_OP[0]
V3_OP[2] V3_OP[1] V3_OP[0]
V4_OP[2] V4_OP[1] V4_OP[0]
V5_OP[2] V5_OP[1] V5_OP[0]
V6_OP[2] V6_OP[1] V6_OP[0]
V7_OP[2] V7_OP[1] V7_OP[0]
X
X
X
En_EOC
X
EN_CHG
Prog_
ICHG[2]
Prog_
EOC[0]
Prog_
ICHG[1]
Prog_
VRSTRT[1]
Prog_
ICHG[0]
Prog_
VRSTRT[0]
LDO Mode Fullrate PRECHG
Tout_
ConstV
APU_TSD_
EN
Bad_Batt
PS_HOLD
_DELAY
(1) X = Not Used
(R/O) = Bits are Read Only type.
Codes other than those shown in the table are disallowed.
(2) Note that for Serial Interface operation and thus register control, LDO2 must be active to provide the power for the internal logic.
LDO Output Voltage Programming
The following table summarizes the supported output voltages for the LP3918. Default voltages after startup are
highlighted in bold.
Data Code
(Reg 01 - 07)
8h'00
8h'01
8h'02
8h'03
8h'04
LDO1
V
1.5
1.8
1.85
2.5
2.6
LDO2
V
2.5
2.6
VLDO3
V
LDO4
V
1.5
1.8
1.85
2.5
2.6
LDO5
V
LDO6
V
LDO7
V
1.5
1.8
1.85
2.5
2.6
14
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