LP3918 Datasheet, PDF (29/39 Pages) National Semiconductor (TI) – Battery Charge Management and Regulator Unit

LP3918
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BIT
0
SNVS476D – AUGUST 2007 – REVISED MAY 2013
Table 21. Register Address 8h'1C: Misc⁽¹⁾ (continued)
NAME
PWR_HOLD
DELAY
FUNCTION (if bit = '1')
1b'0: If PWR_HOLD is low for 35ms the device will shutdown.
(Default)
1b'1: If PWR_HOLD is low for 350ms the device will shutdown.
I²C Compatible Serial Bus Interface
INTERFACE BUS OVERVIEW
The I²C compatible synchronous serial interface provides access to the programmable functions and registers on
the device.
This protocol uses a two-wire interface for bi-directional communications between the IC’s connected to the bus.
The two interface lines are the Serial Data Line (SDA), and the Serial Clock Line (SCL). These lines should be
connected to a positive supply, via a pull-up resistor of 1.5KΩ, and remain HIGH even when the bus is idle.
Every device on the bus is assigned a unique address and acts as either a Master or a Slave depending on
whether it generates or receives the serial clock (SCL).
DATA TRANSACTIONS
One data bit is transferred during each clock pulse. Data is sampled during the high state of the serial clock
(SCL). Consequently, throughout the clock’s high period, the data should remain stable. Any changes on the
SDA line during the high state of the SCL and in the middle of a transaction, aborts the current transaction. New
data should be sent during the low SCL state. This protocol permits a single data line to transfer both
command/control information and data using the synchronous serial clock.
SDA
SCL
Data Line
Stable:
Data Valid
Change
of Data
Allowed
Figure 14. Bit Transfer
Each data transaction is composed of a Start Condition, a number of byte transfers (set by the software) and a
Stop Condition to terminate the transaction. Every byte written to the SDA bus must be 8 bits long and is
transferred with the most significant bit first. After each byte, an Acknowledge signal must follow. The following
sections provide further details of this process.
START AND STOP
The Master device on the bus always generates the Start and Stop Conditions (control codes). After a Start
Condition is generated, the bus is considered busy and it retains this status until a certain time after a Stop
Condition is generated. A high-to-low transition of the data line (SDA) while the clock (SCL) is high indicates a
Start Condition. A low-to-high transition of the SDA line while the SCL is high indicates a Stop Condition.
SDA
SCL
S
START CONDITION
P
STOP CONDITION
Figure 15. Start and Stop Conditions
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