MSP430FG439 Datasheet, PDF (55/88 Pages) Texas Instruments – Mixed-Signal Microcontrollers

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MSP430FG439, MSP430FG438, MSP430FG437
SLAS380D – APRIL 2004 – REVISED NOVEMBER 2014
6.10 Input/Output Schematics
6.10.1 Port P1, P1.0 to P1.5, Input/Output With Schmitt Trigger
DVSS
DVSS
CAPD.x
P1SEL.x
P1DIR.x
Direction Control
From Module
P1OUT.x
Module X OUT
P1IN.x
Module X IN
0
1
0
1
EN
D
Pad Logic
0: Input
1: Output
Bus
Keeper
P1.0/TA0
P1.1/TA0/MCLK
P1.2/TA1
P1.3/TBOUTH/SVSOUT
P1.4/TBCLK/SMCLK
P1.5/TACLK/ACLK
P1IRQ.x
P1IE.x
P1IFG.x
EN
Q
Set
Interrupt
Edge
Select
Note: 0 ≤ x ≤ 5
Note: Port function is active if CAPD.x = 0
P1IES.x P1SEL.x
PnSEL.x
P1SEL.0
PnDIR.x
P1DIR.0
Direction
Control
From Module
P1DIR.0
PnOUT.x
P1OUT0
Module X
OUT
Out0 sig.⁽¹⁾
P1SEL.1
P1SEL.2
P1DIR.1
P1DIR.2
P1DIR.1
P1DIR.2
P1OUT.1
P1OUT.2
MCLK
Out1 sig.⁽¹⁾
P1SEL.3
P1DIR.3
P1DIR.3
P1OUT.3
SVSOUT
P1SEL.4
P1DIR.4
P1DIR.4
P1OUT.4
SMCLK
P1SEL.5
P1DIR.5
P1DIR5
P1OUT.5
ACLK
(1) Timer_A
(2) Timer_B
PnIN.x
P1IN.0
P1IN.1
P1IN.2
P1IN.3
P1IN.4
P1IN.5
Module X IN
CCI0A ⁽¹⁾
CCI0B ⁽¹⁾
CCI1A ⁽¹⁾
TBOUTH ⁽²⁾
TBCLK ⁽²⁾
TACLK ⁽¹⁾
PnIE.x
P1IE.0
P1IE.1
P1IE.2
P1IE.3
P1IE.4
P1IE.5
PnIFG.x
P1IFG.0
P1IFG.1
P1IFG.2
P1IFG.3
P1IFG.4
P1IFG.5
PnIES.x
P1IES.0
P1IES.1
P1IES.2
P1IES.3
P1IES.4
P1IES.5
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Detailed Description
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