MSP430FG439 Datasheet, PDF (48/88 Pages) Texas Instruments – Mixed-Signal Microcontrollers

MSP430FG439, MSP430FG438, MSP430FG437
SLAS380D – APRIL 2004 – REVISED NOVEMBER 2014
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6.9 Peripherals
Peripherals are connected to the CPU through data, address, and control buses and can be handled using
all instructions. For complete module descriptions, see the MSP430x4xx Family User's Guide (SLAU056).
6.9.1 DMA Controller
The DMA controller allows movement of data from one memory address to another without CPU
intervention. For example, the DMA controller can be used to move data from the ADC12 conversion
memory to RAM. Using the DMA controller can increase the throughput of peripheral modules. The DMA
controller reduces system power consumption by allowing the CPU to remain in sleep mode without
having to awaken to move data to or from a peripheral.
6.9.2 Oscillator and System Clock
The clock system in the MSP430FG43x family of devices is supported by the FLL+ module, which
includes support for a 32768-Hz watch crystal oscillator, an internal digitally-controlled oscillator (DCO),
and a high frequency crystal oscillator. The FLL+ clock module is designed to meet the requirements of
both low system cost and low power consumption. The FLL+ features digital frequency locked loop (FLL)
hardware that, in conjunction with a digital modulator, stabilizes the DCO frequency to a programmable
multiple of the watch crystal frequency. The internal DCO provides a fast turn-on clock source and
stabilizes in less than 6 µs. The FLL+ module provides the following clock signals:
• Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high-frequency crystal
• Main clock (MCLK), the system clock used by the CPU
• Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules
• ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, or ACLK/8
6.9.3 Brownout, Supply Voltage Supervisor
The brownout circuit is implemented to provide the proper internal reset signal to the device during power-
on and power-off. The supply voltage supervisor (SVS) circuitry detects if the supply voltage drops below
a user selectable level and supports both supply voltage supervision (the device is automatically reset)
and supply voltage monitoring (the device is not automatically reset).
The CPU begins code execution after the brownout circuit releases the device reset. However, V_CC may
not have ramped to V_CC(min) at that time. The user must make sure that the default FLL+ settings are not
changed until V_CC reaches V_CC(min). If desired, the SVS circuit can be used to determine when V_CC
reaches V_CC(min).
6.9.4 Digital I/O
There are six 8-bit I/O ports implemented—ports P1 through P6:
• All individual I/O bits are independently programmable.
• Any combination of input, output, and interrupt conditions is possible.
• Edge-selectable interrupt input capability for all the eight bits of ports P1 and P2.
• Read and write access to port-control registers is supported by all instructions
6.9.5 Basic Timer1
The Basic Timer1 has two independent 8-bit timers that can be cascaded to form a 16-bit timer/counter.
Both timers can be read and written by software. The Basic Timer1 can be used to generate periodic
interrupts and clock for the LCD module.
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Detailed Description
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