MSP430FG439 Datasheet, PDF (53/88 Pages) Texas Instruments – Mixed-Signal Microcontrollers

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MSP430FG439, MSP430FG438, MSP430FG437
SLAS380D – APRIL 2004 – REVISED NOVEMBER 2014
PERIPHERAL
ADC12
(Memory control
registers require byte
access)
USART0
(UART or SPI mode)
Comparator_A
BrownOUT, SVS
FLL+ Clock
Basic Timer1
Port P6
Port P5
Table 6-13. Peripherals With Byte Access (continued)
REGISTER NAME
ADC memory-control register 15
ADC memory-control register 14
ADC memory-control register 13
ADC memory-control register 12
ADC memory-control register 11
ADC memory-control register 10
ADC memory-control register 9
ADC memory-control register 8
ADC memory-control register 7
ADC memory-control register 6
ADC memory-control register 5
ADC memory-control register 4
ADC memory-control register 3
ADC memory-control register 2
ADC memory-control register 1
ADC memory-control register 0
Transmit buffer
Receive buffer
Baud rate
Baud rate
Modulation control
Receive control
Transmit control
USART control
Comparator_A port disable
Comparator_A control 2
Comparator_A control 1
SVS control register (Reset by brownout signal)
FLL+ Control 1
FLL+ Control 0
System clock frequency control
System clock frequency integrator
System clock frequency integrator
BT counter 2
BT counter 1
BT control
Port P6 selection
Port P6 direction
Port P6 output
Port P6 input
Port P5 selection
Port P5 direction
Port P5 output
Port P5 input
ACRONYM
ADC12MCTL15
ADC12MCTL14
ADC12MCTL13
ADC12MCTL12
ADC12MCTL11
ADC12MCTL10
ADC12MCTL9
ADC12MCTL8
ADC12MCTL7
ADC12MCTL6
ADC12MCTL5
ADC12MCTL4
ADC12MCTL3
ADC12MCTL2
ADC12MCTL1
ADC12MCTL0
U0TXBUF
U0RXBUF
U0BR1
U0BR0
U0MCTL
U0RCTL
U0TCTL
U0CTL
CAPD
CACTL2
CACTL1
SVSCTL
FLL_CTL1
FLL_CTL0
SCFQCTL
SCFI1
SCFI0
BTCNT2
BTCNT1
BTCTL
P6SEL
P6DIR
P6OUT
P6IN
P5SEL
P5DIR
P5OUT
P5IN
OFFSET
08Fh
08Eh
08Dh
08Ch
08Bh
08Ah
089h
088h
087h
086h
085h
084h
083h
082h
081h
080h
077h
076h
075h
074h
073h
072h
071h
070h
05Bh
05Ah
059h
056h
054h
053h
052h
051h
050h
047h
046h
040h
037h
036h
035h
034h
033h
032h
031h
030h
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Detailed Description
53