MSP430FG439 Datasheet, PDF (35/88 Pages) Texas Instruments – Mixed-Signal Microcontrollers

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MSP430FG439, MSP430FG438, MSP430FG437
SLAS380D – APRIL 2004 – REVISED NOVEMBER 2014
5.31 12-Bit DAC, Reference Input Specifications
over recommended operating free-air temperature range (unless otherwise noted)
Ve_REF+
PARAMETER
TEST CONDITIONS
Reference input voltage ^{DAC12IR = 0(1) (2)}
range
DAC12IR = 1^{(3) (4)}
DAC12_0 IR = DAC12_1 IR = 0
V_CC
2.2 V, 3 V
MIN
TYP
MAX UNIT
AV_CC / 3 AV_CC + 0.2 _V
AV_CC AV_CC + 0.2
20
MΩ
Ri_(VREF+), Reference input
(Ri_(VeREF+) resistance
DAC12_0 IR = 1, DAC12_1 IR = 0
DAC12_0 IR = 0, DAC12_1 IR = 1
40
48
2.2 V, 3 V
40
48
DAC12_0 IR = DAC12_1 IR =1,
DAC12_0 SREFx = DAC12_1 SREFx⁽⁵⁾
20
24
56
56 _kΩ
28
(1) For a full-scale output, the reference input voltage can be as high as 1/3 of the maximum output voltage swing (AV_CC).
(2) The maximum voltage applied at reference input voltage terminal Ve_REF+ = [AV_CC – V_E(O)] / [3 × (1 + E_G)].
(3) For a full-scale output, the reference input voltage can be as high as the maximum output voltage swing (AV_CC).
(4) The maximum voltage applied at reference input voltage terminal Ve_REF+ = [AV_CC – V_E(O)] / (1 + E_G).
(5) When DAC12IR = 1 and DAC12SREFx = 0 or 1 for both channels, the reference input resistive dividers for each DAC are in parallel,
reducing the reference input resistance.
5.32 12-Bit DAC, Dynamic Specifications
V_ref = V_CC, DAC12IR = 1, over recommended operating free-air temperature range (unless otherwise noted) (see Figure 5-25
and Figure 5-26)
PARAMETER
t_ON
DAC12 on time
TEST CONDITIONS
DAC12_xDAT = 800h,
Error_V(O) < ±0.5 LSB⁽¹⁾
(see Figure 5-25)
DAC12AMPx = 0 → {2, 3, 4}
DAC12AMPx = 0 → {5, 6}
DAC12AMPx = 0 → 7
V_CC
2.2 V, 3 V
MIN TYP MAX UNIT
60 120
15 30 µs
6 12
t_S(FS)
Settling time,
full scale
DAC12_xDAT =
80h→F7Fh→80h
DAC12AMPx = 2
DAC12AMPx = 3, 5
DAC12AMPx = 4, 6, 7
2.2 V, 3 V
100 200
40 80 µs
15 30
t_S(C–C)
Settling time,
code to code
DAC12_xDAT =
3F8h→408h→3F8h
BF8h→C08h→BF8h
DAC12AMPx = 2
DAC12AMPx = 3, 5
DAC12AMPx = 4, 6, 7
2.2 V, 3 V
5
2
µs
1
SR
Slew rate
DAC12_xDAT =
80h→ F7Fh→ 80h⁽²⁾
DAC12AMPx = 2
DAC12AMPx = 3, 5
DAC12AMPx = 4, 6, 7
2.2 V, 3 V
0.05 0.12
0.35 0.7
1.5 2.7
V/µs
Glitch energy,
full scale
DAC12_xDAT =
80h→ F7Fh→ 80h
DAC12AMPx = 2
DAC12AMPx = 3, 5
DAC12AMPx = 4, 6, 7
2.2 V, 3 V
10
10
nV-s
10
(1) R_Load and C_Load connected to AV_SS (not AV_CC/2) in Figure 5-25.
(2) Slew rate applies to output voltage steps ≥ 200 mV.
DAC Output
RLoad = 3 k _W
ILoad
AVCC
2
R _O/P(DAC12.x)
CLoad = 100pF
V _OUT
Conversion 1
Glitch
Energy
Conversion 2
+/- 1/2 LSB
Conversion 3
+/- 1/2 LSB
tsettleLH
Figure 5-25. Settling Time and Glitch Energy Testing
tsettleHL
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Specifications
35