MSP430FG439 Datasheet, PDF (28/88 Pages) Texas Instruments – Mixed-Signal Microcontrollers

MSP430FG439, MSP430FG438, MSP430FG437
SLAS380D – APRIL 2004 – REVISED NOVEMBER 2014
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5.24 12-Bit ADC, Built-In Reference
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
V_REF+
AV_CC(min)
Positive built in reference
voltage output
AV_CC minimum voltage,
Positive built in reference active
REF2_5V = 1 for 2.5 V,
I_VREF+max ≤ I_VREF+ ≤ I_VREF+min
REF2_5V = 0 for 1.5 V,
I_VREF+max ≤ I_VREF+ ≤ I_VREF+min
REF2_5V = 0,
I_VREF+max ≤ I_VREF+ ≤ I_VREF+min
REF2_5V = 1,
I_VREF+min ≥ I_VREF+ ≥ –0.5 mA
REF2_5V = 1,
I_VREF+min ≥ I_VREF+ ≥ – 1 mA
I_VREF+
Load current out of V_REF+
terminal
V_CC
3V
2.2 V, 3 V
2.2 V
3V
MIN TYP MAX UNIT
2.4
2.5
2.6
V
1.44
1.5 1.56
2.2
2.8
V
2.9
0.01
–0.5
mA
0.01
–1
I_L(VREF)+
Load-current regulation, V_REF+
terminal
I_VREF+ = 500 µA ± 100 µA,
Analog input voltage ≈ 0.75 V,
REF2_5V = 0
I_VREF+ = 500 µA ± 100 µA,
Analog input voltage ≈ 1.25 V,
REF2_5V = 1
2.2 V
3V
3V
±2
LSB
±2
±2 LSB
I_DL(VREF)+
Load current regulation, V_REF+
terminal
I_VREF+ = 100 µA → 900 µA,
C_VREF+ = 5 µF, ax ≈ 0.5 × V_REF+,
Error of conversion result ≤ 1 LSB
3V
20 ns
C_VREF+
T_REF+
t_REFON
Capacitance at pin V_REF+ ⁽¹⁾
REFON =1,
0 mA ≤ I_VREF+ ≤ I_VREF+max
Temperature coefficient of built- I_VREF+ is a constant in the range of
in reference
0 mA ≤ I_VREF+ ≤ 1 mA
Settle time of internal reference I_VREF+ = 0.5 mA, C_VREF+ = 10 µF,
voltage (see Figure 5-18 ) ⁽²⁾ V_REF+ = 1.5 V, V_AVCC = 2.2 V
2.2 V, 3 V
2.2 V, 3 V
5
10
µF
±100 ppm/°C
17 ms
(1) The internal buffer operational amplifier and the accuracy specifications require an external capacitor. All INL and DNL tests uses two
capacitors between pins V_REF+ and AV_SS and V_REF-–/V_eREF– and AV_SS: 10 µF tantalum and 100 nF ceramic.
(2) The condition is that the error in a conversion started after t_REFON is less than ±0.5 LSB. The settling time depends on the external
capacitive load.
C_VREF+
100 mF
10 mF
t_REFON » .66 x C_VREF+ [ms] with C_VREF+ in mF
1 mF
0
1 ms
10 ms
100 ms
t_REFON
Figure 5-18. Typical Settling Time of Internal Reference t_REFON vs External Capacitor on V_REF+
28
Specifications
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