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MSP430FG439 Datasheet, PDF (27/88 Pages) Texas Instruments – Mixed-Signal Microcontrollers
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MSP430FG439, MSP430FG438, MSP430FG437
SLAS380D – APRIL 2004 – REVISED NOVEMBER 2014
5.22 12-Bit ADC, Power Supply and Input Range Conditions(1)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
AVCC
V(P6.x/Ax)
IADC12
Analog supply voltage
Analog input voltage range(2)
Operating supply current into the
AVCC terminal(3)
AVCC and DVCC are connected together,
AVSS and DVSS are connected together,
V(AVSS) = V(DVSS) = 0 V
All external Ax terminals, Analog inputs selected in
ADC12MCTLx register and P6Sel.x = 1,
V(AVSS) ≤ VAx ≤ V(AVCC)
fADC12CLK = 5.0 MHz,
ADC12ON = 1, REFON = 0,
SHT0 = 0, SHT1 = 0, ADC12DIV = 0
VCC = 2.2 V
VCC = 3 V
2.2
3.6 V
0
VAVCC V
0.65
1.3
mA
0.8
1.6
IREF+
Operating supply current into the
AVCC terminal(4)
fADC12CLK = 5.0 MHz,
ADC12ON = 0,
REFON = 1, REF2_5V = 1
fADC12CLK = 5.0 MHz,
ADC12ON = 0
REFON = 1, REF2_5V = 0
VCC = 3 V
VCC = 2.2 V
VCC = 3 V
0.5
0.8 mA
0.5
0.8
mA
0.5
0.8
CI
Input capacitance
Only one terminal can be selected at one
time, Ax
VCC = 2.2 V
40 pF
RI
Input MUX ON resistance
0 V ≤ VAx ≤ VAVCC
VCC = 3 V
2000 Ω
(1) The leakage current is defined in the leakage current table with Ax parameter.
(2) The analog input voltage range must be within the selected reference voltage range VR+ to VR– for valid conversion results.
(3) The internal reference supply current is not included in current consumption parameter IADC12.
(4) The internal reference current is supplied via terminal AVCC. Consumption is independent of the ADC12ON control bit, unless a
conversion is active. The REFON bit enables to settle the built-in reference before starting an A/D conversion.
5.23 12-Bit ADC, External Reference(1)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
VeREF+
Positive external reference
voltage input
VeREF+ > VREF–/VeREF– (2)
1.4
VAVCC V
VREF–/VeREF–
Negative external reference
voltage input
VeREF+ > VREF–/VeREF– (3)
0
1.2 V
(VeREF+ –
VREF–/VeREF–)
Differential external reference
voltage input
VeREF+ > VREF–/VeREF– (4)
1.4
IVeREF+
Static input current
0 V ≤ VeREF+ ≤ VAVCC
VCC = 2.2 V, 3 V
IVREF–/VeREF–
Static input current
0 V ≤ VeREF– ≤ VAVCC
VCC = 2.2 V, 3 V
VAVCC V
±1 µA
±1 µA
(1) The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, CI, is also the
dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy.
(2) The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
(3) The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
(4) The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
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Specifications
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