MSP430FG439 Datasheet, PDF (44/88 Pages) Texas Instruments – Mixed-Signal Microcontrollers

MSP430FG439, MSP430FG438, MSP430FG437
SLAS380D – APRIL 2004 – REVISED NOVEMBER 2014
www.ti.com
6.5 Special Function Registers (SFRs)
The MSP430 SFRs are located in the lowest address space and are organized as byte-mode registers.
SFRs should be accessed with byte instructions.
Legend
rw
rw-0, rw-1
rw-(0), rw-1
Bit can be read and written.
Bit can be read and written. It is Reset or Set by PUC.
Bit can be read and written. It is Reset or Set by POR.
SFR bit is not present in device.
6.5.1 Interrupt Enable Registers 1 and 2
7
UTXIE0
rw–0
6
URXIE0
rw–0
Figure 6-1. Interrupt Enable Register 1 (Address = 0h)
5
4
3
ACCVIE
NMIIE
rw–0
rw–0
2
1
OFIE
rw–0
0
WDTIE
rw–0
BIT FIELD
7
UTXIE0
6
URXIE0
5
ACCVIE
4
NMIIE
1
OFIE
0
WDTIE
Table 6-4. Interrupt Enable Register 1 Field Descriptions
TYPE
RW
RW
RW
RW
RW
RW
RESET
0h
0h
0h
0h
0h
0h
DESCRIPTION
USART0: UART and SPI transmit-interrupt enable
USART0: UART and SPI receive-interrupt enable
Flash access violation interrupt enable
Nonmaskable-interrupt enable
Oscillator-fault-interrupt enable
Watchdog-timer interrupt enable. Inactive if watchdog mode is selected.
Active if watchdog timer is configured as a general-purpose timer.
Figure 6-2. Interrupt Enable Register 2 (Address = 1h)
7
6
5
4
3
2
1
0
BTIE
rw–0
BIT FIELD
7
BTIE
Table 6-5. Interrupt Enable Register 2 Field Descriptions
TYPE
RW
RESET DESCRIPTION
0h
Basic timer interrupt enable
44
Detailed Description
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