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| MSP430FG439 Datasheet, PDF (43/88 Pages) Texas Instruments – Mixed-Signal Microcontrollers | |||
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www.ti.com
MSP430FG439, MSP430FG438, MSP430FG437
SLAS380D â APRIL 2004 â REVISED NOVEMBER 2014
6.4 Interrupt Vector Addresses
The interrupt vectors and the power-up start address are located in the address range 0FFFFh to 0FFC0h.
The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
Table 6-3. Interrupt Sources, Flags, and Vectors of MSP430FG43x Configurations
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM
INTERRUPT
WORD
ADDRESS
PRIORITY
Power-Up
External Reset
Watchdog
Flash Memory
NMI
Oscillator Fault
Flash Memory Access Violation
Timer_B3
WDTIFG
KEYV (1)
NMIIFG (1)
OFIFG (1)
ACCVIFG (1)
TBCCR0 CCIFG0(3)
Reset
(Non)maskable (2)
(Non)maskable
(Non)maskable
Maskable
0FFFEh
0FFFCh
0FFFAh
15, highest
14
13
Timer_B3
TBCCR1 CCIFG1 and TBCCR2 CCIFG2,
TBIFG(1) (3)
Maskable
0FFF8h
12
Comparator_A
CAIFG
Maskable
0FFF6h
11
Watchdog Timer
WDTIFG
Maskable
0FFF4h
10
USART0 Receive
URXIFG0
Maskable
0FFF2h
9
USART0 Transmit
ADC12
Timer_A3
UTXIFG0
ADC12IFG (1) (3)
TACCR0 CCIFG0(3)
Maskable
0FFF0h
8
Maskable
0FFEEh
7
Maskable
0FFECh
6
Timer_A3
TACCR1 CCIFG1 and TACCR2 CCIFG2,
TAIFG(1) (3)
Maskable
0FFEAh
5
I/O Port P1 (Eight Flags)
P1IFG.0 to P1IFG.7(1) (3)
Maskable
0FFE8h
4
DAC12 DMA
DAC12.0IFG, DAC12.1IFG, DMA0IFG(1) (3)
Maskable
0FFE6h
3
I/O Port P2 (Eight Flags)
P2IFG.0 to P2IFG.7 (1) (3)
0FFE4h
2
Maskable
0FFE2h
1
Basic Timer1
BTIFG
Maskable
0FFE0h
0, lowest
(1) Multiple source flags
(2) (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.
(3) Interrupt flags are located in the module.
Copyright © 2004â2014, Texas Instruments Incorporated
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Detailed Description
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