MSP430FG439 Datasheet, PDF (45/88 Pages) Texas Instruments – Mixed-Signal Microcontrollers

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MSP430FG439, MSP430FG438, MSP430FG437
SLAS380D – APRIL 2004 – REVISED NOVEMBER 2014
6.5.2 Interrupt Flag Registers 1 and 2
7
UTXIFG0
rw–1
6
URXIFG0
rw–0
Figure 6-3. Interrupt Flag Register 1 (Address = 2h)
5
4
3
NMIIFG
rw–0
2
1
OFIFG
rw–1
0
WDTIFG
rw–(0)
BIT FIELD
7
UTXIFG0
6
URXIFG0
4
NMIIFG
1
OFIFG
0
WDTIFG
TYPE
RW
RW
RW
RW
RW
Table 6-6. Interrupt Flag Register 1 Field Descriptions
RESET
1h
0h
0h
1h
0h
DESCRIPTION
USART0: UART and SPI transmit flag
USART0: UART and SPI receive flag
Set by RST/NMI pin
Flag set on oscillator fault
Set on watchdog timer overflow (in watchdog mode) or security key violation
Reset on V_CC power-on or a reset condition at the RST/NMI pin in reset mode
Figure 6-4. Interrupt Flag Register 2 (Address = 3h)
7
6
5
4
3
2
1
0
BTIFG
rw–0
BIT FIELD
7
BTIFG
TYPE
RW
Table 6-7. Interrupt Flag Register 2 Field Descriptions
RESET DESCRIPTION
0h
Basic timer flag
6.5.3 Module Enable Registers 1 and 2
Figure 6-5. Module Enable Register 1 (Address = 4h)
7
6
5
4
3
2
1
0
UTXE0
URXE0
USPIE0
rw–0
rw–0
BIT FIELD
7
UTXE0
URXE0
6
USPIE0
TYPE
RW
RW
RW
Table 6-8. Module Enable Register 1 Field Descriptions
RESET
0h
0h
0h
DESCRIPTION
USART0: UART mode transmit enable
USART0: UART mode receive enable
USART0: SPI mode transmit and receive enable
Figure 6-6. Module Enable Register 2 (Address = 5h)
7
6
5
4
3
2
1
0
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Detailed Description
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