TLK2208B Datasheet, PDF (9/40 Pages) Texas Instruments – 8-PORT GIGABIT ETHERNET TRANCSEIVER

TLK2208B
8ĆPORT GIGABIT ETHERNET TRANSCEIVER
SLLS578D − AUGUST 2003 − REVISED SEPTEMBER 2006
SIGNAL
RDFE9
RDHG[7:0]
RDHG8
RDHG9
LOCATION
T8
T12, U12,
T11, U11,
T10, U10,
T9, U9
U13
T13
TYPE
LVCMOS
output
LVCMOS
output
LVCMOS
output
LVCMOS
output
DESCRIPTION
Receive data 9, channels E and F. The parallel data is clocked out of the transceiver on the rising and
falling edges of the receive clock. In multiplexed channel mode, when CODE = low, this terminal is the
10th bit of a 10-bit word received.
In nibble interface mode, when CODE = low, this terminal is the 5th and 10th bits of a 10-bit word received
on channel F.
This terminal is internally series terminated to provide direct connection to a 50-Ω transmission line.
Receive data channels G and H. The parallel data is clocked out of the transceiver on the rising and
falling edges of the receive clock.
In multiplexed channel mode, data for channel H is aligned to the rising edge of RCLK and data for
channel G is aligned to the falling edge of RCLK (see Figure 6 for clarity).
In nibble mode, data is output least-significant nibble first, aligned to the falling edge of the receive clock,
followed by the most significant nibble aligned to the rising edge. Channel G is output on RDHG[4:0]
and channel H is output on RDHG[9:5]. When CODE = high, RDHG3 acts as the K-flag bit for channel
G on the rising edge of RCLK.
These terminals are internally series terminated to provide direct connection to a 50-Ω transmission
line.
Receive data/K-flag, channels G and H. The parallel data is clocked out of the transceiver on the rising
and falling edges of receive clock.
In multiplexed channel mode, when CODE = low, this terminal is the 9th bit of a 10-bit word received.
When CODE = high, this terminal acts as the K-flag bit. When RDFE8 = high, this terminal indicates
that the data on RDHG[7:0] is a K-character.
In nibble interface mode, when CODE = low, this terminal is the 4th and 9th bits of a 10-bit word received
on channel H. When CODE = high, this terminal acts as the 4th bit on the falling edge and as the K-flag
bit on the rising edge for channel H. When RDHG8 = high, this terminal indicates that the data on
RDHG[7:0], output on the rising and falling edges of the receive clock, is a K-character.
This terminal is internally series-terminated to provide direct connection to a 50-Ω transmission line.
Receive data 9, channels G and H. The parallel data is clocked out of the transceiver on the rising and
falling edges of the receive clock.
In multiplexed channel mode, when CODE = low, this terminal is the 10th bit of a 10-bit word received.
In nibble interface mode, when CODE = low, this terminal is the 5th and 10th bits of a 10-bit word received
on channel H.
This terminal is internally series-terminated to provide direct connection to a 50-Ω transmission line.
Management Data Interface Signals
SIGNAL LOCATION
MDIO
J1
MDC
H3
DVAD[4:0]
D12, D11,
P13, R13,
R12
TYPE
LVCMOS
I/O with
P/U
LVCMOS
input
LVCMOS
input with
P/D
DESCRIPTION
Management data I/O. MDIO is the bidirectional serial data path for the transfer of management data
to and from the protocol device.
Management data clock. MDC is the clock reference for the transfer of management data to and from
the protocol device.
Management address. Device address: DVAD[4:0] is the externally set physical address given to this
device, used to distinguish one device from another. This address is latched on the rising edge of
RESET.
JTAG Interface Signals
SIGNAL
TCK
TDI
LOCATION
C10
C9
TYPE
LVCMOS
input
LVCMOS
input with
P/U
DESCRIPTION
Test clock. IEEE 1149.1 (JTAG) TCK is used to clock state information and test data into and out of
the device during the operation of the test port.
Test data input. IEEE 1149.1 (JTAG) TDI is used to shift test data and test instructions into the device
serially during the operation of the test port.
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