TLK2208B Datasheet, PDF (36/40 Pages) Texas Instruments – 8-PORT GIGABIT ETHERNET TRANCSEIVER

TLK2208B
8ĆPORT GIGABIT ETHERNET TRANSCEIVER
SLLS578D − AUGUST 2003 − REVISED SEPTEMBER 2006
LVCMOS output switching characteristics over recommended operating conditions (unless
otherwise noted)
PARAMETER
TEST CONDITION
MIN NOM MAX UNIT
tr
Clock and data rise time
80% to 20% output voltage, C = 10 pF, See Figure 14
0.3
80% to 20% output voltage, C = 10 pF, See Figure 14
0.3
1.5
ns
1.5
tf
Clock and data fall time
20% to 80% output voltage, C = 10 pF, See Figure 14 0.36
20% to 80% output voltage, C = 10 pF, See Figure 14 0.36
1.8
ns
1.8
tsu
RD[9:0] setup prior to RCLK
transition high or low
Timing relative to 0.5 VDDQ, See Figure 14
1.4
ns
th
RD[9:0] hold after RCLK transition
high or low
Timing relative to 0.5 VDDQ, See Figure 14
0.8
ns
RCLK, RBC[A:G]
tr
tf
RDxx[9:0]
tsu
tsu
th
Figure 14. LVCMOS Receive Output Timing requirements
VDDQ/2
th
LVCMOS input timing requirements over recommended operating conditions (unless otherwise
noted)
PARAMETER
TEST CONDITION
MIN NOM† MAX UNIT
TDxx[9:0] setup prior to TCLKx transition Timing relative to 0.5 VDDQ
tsu
high or low
See Figure 15
1.4
ns
th
TDxx[9:0] hold after TCLKx transition high Timing relative to 0.5 VDD
or low
See Figure 15
0.0
ns
t(Pulse)‡ TCLKx clock period divided by 2
Timing relative to 0.5 VDDQ,
See Figure 16
3.85
† _{All typical values are at 25°C and with a nominal supply.}
‡ _{TCLKB is assumed to be frequency locked to REFCLK with only phase differences.}
NOTE: Timings valid for VIH no less than 80% of VDDQ and VIL no higher than 20% VDDQ.
5 ns
t(Pulse)
t(Pulse)
TCLKx
VDDQ/2
tr
tf
TDxx[9:0] TDxx[9:5]
tsu
th
tsu
th
TDxx[4:0]
Figure 15. LVCMOS Source Centered Data Input Timing Requirements
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