TLK2208B Datasheet, PDF (10/40 Pages) Texas Instruments – 8-PORT GIGABIT ETHERNET TRANCSEIVER

TLK2208B
8ĆPORT GIGABIT ETHERNET TRANSCEIVER
SLLS578D − AUGUST 2003 − REVISED SEPTEMBER 2006
TDO
TMS
TRST
C7
LVCMOS Test data output. IEEE 1149.1 (JTAG) TDO is used to shift test data and test instructions out of the
output device serially during operation of the test port. When the JTAG port is not in use, TDO is in a
high-impedance state.
C11
LVCMOS Test mode select. IEEE 1149.1 (JTAG) TMS is used to control the state of the internal test-port
input controller.
with P/U
D8
LVCMOS JTAG reset. IEEE 1149.1 (JTAG) TRST is used to reset the internal JTAG controller.
input
with P/U
Miscellaneous Signals
SIGNAL
CODE
LOCATION
J2
CV_DIS_EN
J3
RESET
G3
LPBK
D7
MODE1
MODE0
P12, P11
ENABLE
D13
TCLKSEL
D9
BUSYEN
P9
PLL_LOCK
R11
TYPE
LVCMOS
input
with P/D
LVCMOS
input
with P/D
LVCMOS
input with
P/D
LVCMOS
input
with P/D
LVCMOS
input
with P/D
LVCMOS
input
with P/U
LVCMOS
input
LVCMOS
input
with P/U
LVCMOS
output
DESCRIPTION
Encode enable. When high, the 8b/10b encoder and decoder are enabled. The logic value of this
terminal is logically ORed with MDIO register 17.7 (8b/10b_EN).
Code violation/disparity error code enable. When CV_DIS_EN is high, the outputs RDxx[9:0] are
set to 1 when a code violation or disparity error is detected. The logic value of this terminal is logically
ORed with the MDIO register 17.14 (CVDispEn).
This requires CODE to be enabled.
Chip reset (FIFO clear). Pulling this terminal high recenters the transmit skew buffers, recenters
receive channel synchronization FIFOs, and resets MDIO flags.
Serial loopback enable. When asserted high, the outputs of the 8b/10b encoder are looped into the
inputs of the 8b/10b decoder for each channel. The serial transmit outputs are held in the
high-impedance state and the serial inputs are ignored.
Configuration terminals. These terminals put the device under one of the following operation modes:
MODE[1:0]
00 – Multiplexed channel mode
01 – Reserved
10 – Nibble interface mode
11 – Reserved
Device enable. Pulling this terminal high enables all outputs of the device. A low on this terminal
places all outputs for the device in the high-impedance state.
Transfer clock select. This terminal controls clock selection mode between synchronized and
independent channel mode.
In independent channel mode (TCLKSEL = 1) channels are clocked in and out by independent
clocks TLCK[B:H] and RBC[A:H], respectively. In synchronized channel mode (TCLKSEL = 0)
transmit and receive clocks are centered around TCLKB and RCLK/RBCH.
The logic value of this signal is ORed with TransClkMode, MDIO register R17.15.
Busy mode enable. When asserted high, /K28.5/D10.1/ are treated as valid data and passed
through the FIFO. When in the low state it causes high /K28.5/D10.1/ to be treated as an IDLE
sequence that can be deleted.
PLL lock. When asserted high, this terminal provides an indication that sufficient time has elapsed
after a power-cycle or power-down sequence to ensure that PLLs have achieved lock.
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