TLK2208B Datasheet, PDF (24/40 Pages) Texas Instruments – 8-PORT GIGABIT ETHERNET TRANCSEIVER

TLK2208B
8ĆPORT GIGABIT ETHERNET TRANSCEIVER
SLLS578D − AUGUST 2003 − REVISED SEPTEMBER 2006
receive logic(continued)
Table 4. Valid K-Characters
K-CHARACTER
RECEIVE DATA BUS
(RDxx[7:0])
ENCODED K-CODE
NEGATIVE RUNNING
DISPARITY
POSITIVE RUNNING
DISPARITY
K28.0
K28.1
0001 1100
0011 1100
00 1111 0100
00 1111 1001[1]
11 0000 1011
11 0000 0110
K28.2
0101 1100
00 1111 0101
11 0000 1010
K28.3
0111 1100
00 1111 0011
11 0000 1100
K28.4
K28.5
1001 1100
1011 1100
00 1111 0010
00 1111 1010[1]
11 0000 1101
11 0000 0101
K28.6
K28.7
1101 1100
1111 1100
00 1111 0110
00 1111 1000[1]
11 0000 1001
11 0000 0111
K23.7
1111 0111
11 1010 1000
00 0101 0111
K27.7
1111 1011
11 0110 1000
00 1001 0111
K29.7
1111 1101
10 1110 1000
01 0001 0111
K30.7
1111 1110
01 1110 1000
NOTE 1: A comma is contained within this K-code.
10 0001 0111
decoder and code violation logic
When the on-chip 8b/10b encoder/decoder is enabled (CODE = high), the reception of K-characters is reported
by the assertion of RDxx8 on each channel. When a code-word error or running-disparity error is detected in
the decoded data on a channel, RDxx[7:0] is asserted and is all 1s (0xFF).
control logic
MDIO management interface
The TLK2208B supports the management-data input/output (MDIO) interface as defined in Clause 22 of the
IEEE 802.3 Ethernet specification. The MDIO allows register-based management and control of the serial links.
Normal operation of the TLK2208B is possible without use of this interface because all of the essential signals
necessary for operations are accessible via the device terminals. However, some additional features are
accessible only through the MDIO.
The MDIO management interface consists of a bidirectional data path (MDIO) and a clock reference (MDC).
The timing required to read from the internal registers is shown in Figure 8; the timing required to write to the
internal registers is shown in Figure 9.
MDC
MDIO
32 1s
Hi-Z
0
1
1
0
A4
A0
R4
R0
0
D15 D0
Preamble
SFD
PHY Address
Data
Idle
Register Address
Read Code
Turn Around
Figure 8. Management Interface Read Timing
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