TLK2208B Datasheet, PDF (32/40 Pages) Texas Instruments – 8-PORT GIGABIT ETHERNET TRANCSEIVER

TLK2208B
8ĆPORT GIGABIT ETHERNET TRANSCEIVER
SLLS578D − AUGUST 2003 − REVISED SEPTEMBER 2006
power-on reset
Upon application of minimum valid power, the TLK2208B generates an internal power-on reset. During the
power-on reset the receive data outputs are placed in the high-impedance state and the recovered receive clock
terminals are held low. The length of the power-on reset cycle is dependent upon the ramp curve of the power
supply . A typical value would be 1 ms after VDD crosses Vth (approx. 1/2 VDD). The power-on reset is sourced
by the digital core supply voltage VDD.
PRBS generator and comparator
The TLK2208B has a built-in 2⁷−1 pseudo-random bit stream (PRBS) self-test function available on each
channel. Compared to all 8b/10b data pattern combinations, the PRBS is a worst-case bit pattern. The self-test
function is enabled using the PRBSEN terminal or setting the PRBS enable bit in the MDIO registers. When the
self-test function is enabled, a PRBS is generated and fed into the 10-bit parallel-to-serial converter input
register. Data on the transmit data bus is ignored during the PRBS test mode. The PRBS pattern is then fed
through the transmit circuitry as if it were normal data and sent out to the transmitter. The output can be sent
to a bit-error rate tester (BERT), the receiver of another TLK2208B channel.
The result from PRBS verification at the RX ports of the device can be read from the MDIO registers 31.15:8.
During PRBS testing (PRBS terminal asserted logic 1), RDxx[9:0] is disregarded.
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