TLK2208B Datasheet, PDF (19/40 Pages) Texas Instruments – 8-PORT GIGABIT ETHERNET TRANCSEIVER

TLK2208B
8ĆPORT GIGABIT ETHERNET TRANSCEIVER
SLLS578D − AUGUST 2003 − REVISED SEPTEMBER 2006
parallel interface modes
The TLK2208B provides two basic operational interface modes controlled by the state of terminals MODE0 and
MODE1. The internal state of these mode terminals can be controlled via MDIO to change the modes of
operation. These operational interface modes are listed in Table 2.
Table 2. Parallel Interface Modes
MODE1
MODE2
OPERATING MODES
Low
Low
Multiplexed channel mode
Low
High Reserved
High
Low
Nibble interface channel mode
High
High Reserved
NOTE: MODE terminals can be overridden via MDIO register 17.6
(MODE_OVR).
Regardless of MODE settings, the channels can be operated in synchronous mode or independent mode. The
channels are operated in synchronous mode when the TCLKSEL terminal (or MDIO register 17.15) is set to a
logic low (default). If either the terminal or the MDIO register is set to a logic high, the channels are operated
in independent mode. See the serializer section for further details.
The clock tolerance compensation, (see the clock tolerance compensation (CTC) section), is enabled by
default and must not be disabled via MDIO while in the multiplexed channel mode.
transmit logic
The transmit logic converts parallel data into an NRZ serial bit stream with a differential VML output at
1.0–1.3 Gbps, dependent on REFCLK and TCLKx frequency. The input to the transmitter can be either an 8-bit
parallel word plus a control (K) bit, or a 10-bit word.
transmit clock interface
The TLK2208B provides two transmit clocking modes as summarized in Table 3. In synchronous channel mode,
all input data for all channels is timed from a single input clock, TCLKB. In independent channel mode, four
clocks are used; input data for each pair of channels is timed with one of these clocks.
In synchronous channel mode, data to be transmitted is latched by both the rising and falling edges of TCLKB.
TCLKB must be frequency synchronous with REFCLK (0 ppm), but may have any phase relationship with
respect to REFCLK.
In independent channel mode, input data for channels A and B is referenced from TCLKB. Input data for
channels C and D is referenced from TCLKD. Input data for channels E and F is referenced from TCLKF, and
lastly input data from channels G and H is referenced from TCLKH. TCLKB, TCLKD, TCLKF and TCLKH are
expected to be the same frequency as the reference clock, REFCLK, but of arbitrary phase.
Table 3. Independent vs Synchronous Mode
TCLKSEL
(TERMINAL)
Low
Don’t Care
High
TransClkMode
MDIO
REGISTER
17.15
OPERATING MODE
Low
Synchronous channel mode
High
Independent channel mode
Don’t Care Independent channel mode
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