TLK2208B Datasheet, PDF (23/40 Pages) Texas Instruments – 8-PORT GIGABIT ETHERNET TRANCSEIVER

TLK2208B
8ĆPORT GIGABIT ETHERNET TRANSCEIVER
SLLS578D − AUGUST 2003 − REVISED SEPTEMBER 2006
receive logic(continued)
clock tolerance compensation (CTC)
The TLK2208B compensates for the possibility that the incoming serial-data rate on any channel can be as
much as 100 ppm faster or slower than the REFCLK frequency (±100 ppm). Each channel independently and
dynamically compensates for any frequency difference by the use of an elasticity buffer. If the incoming data
rate is faster than the REFCLK frequency, the elasticity buffer fills. As it approaches the fill limit, it deletes or
drops a 20-bit IDLE code^[1] found in the gap between Ethernet packets. If the incoming data rate is slower than
the REFCLK, the elasticity buffer empties. As it approaches the empty limit, it adds or inserts a selectable 20-bit
IDLE code found in the gap between Ethernet packets. IDLE code selection defaults to IDLE2, and can be
changed to IDLE1 via MDIO. No running disparity is affected due to either the addition or the deletion of the IDLE
code, as the IDLE code has a balanced number of 1s and 0s. Note that a deletion of a 20-bit IDLE code could
reduce the inter-packet gap below the minimum inter-packet gap of 12 bytes (120 bits).
The CTC function adds or deletes IDLE codes only in the interpacket gap or during autonegotiation. Thus, the
CTC FIFO depth is set to ensure that maximum size Ethernet packets (1540 bytes) can be received
continuously at the frequency offset extremes without loss of data or synchronization. The CTC function can
be disabled chip-wide via the MDIO registers.
When the CTC function is enabled, recovered clocks (RBCx) are buffered versions of the REFCLK.
When the CTC function is not enabled (nibble mode operation only), the recovered clocks for each channel are
one tenth the rate of the clock recovered from the incoming stream.
byte alignment logic
Under default conditions, the TLK2208B uses the IEEE 802.3z-defined 10-bit K28.5 character (comma
character, positive disparity) word alignment scheme^[2]. The following sections explain how this scheme works
and how it realigns itself.
When parallel data is clocked into a parallel-to-serial converter, the byte boundary that was associated with the
parallel data is lost in the serialization of the data. When the serial data is received and converted to parallel
format again, a method is needed to be able to recognize the byte boundary again. Generally this is
accomplished through the use of a synchronization pattern. This is a unique a pattern of 1s and 0s that either
cannot occur as part of valid data or is a pattern that repeats at defined intervals. 8b/10b encoding contains a
character called the comma (001 1111b), which is used by the comma-detect circuit to align the received serial
data back to its original byte boundary. The decoder detects the K28.5 comma, generating a synchronization
signal aligning the data to their 10-bit boundaries for decoding. It then converts the data back into 8-bit data.
It is important to note that the comma can be either 001 1111b or the inverse, 110 0000b, depending on the
running disparity. The TLK2208B decoder detects only the 001 1111b pattern. Therefore, since synchronization
is achieved on the positive comma, two consecutive K-codes containing commas are required to ensure byte
boundary synchronization (see Table 4).
During all operations, the TLK2208B receive clocks (RCLK, RBCx) are a constant duty cycle and frequency.
There are no stretched or shortened clock pulses.
[1] _{IEEE 802.3z specifies an IDLE as a 20-bit code consisting of an IDLE1 code (/K28.5/D5.6/) and an IDLE2 code (/K28.5/D16.2/).}
[2] _{Setting COMMA_DET = 0 by changing its value via MDIO 17.8 disables comma detection, and byte alignment takes place on any bit boundary;}
this permits external byte alignment on different bit sequences, and allows for the use of different bit-balancing algorithms.
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