TLK2208B Datasheet, PDF (29/40 Pages) Texas Instruments – 8-PORT GIGABIT ETHERNET TRANCSEIVER

TLK2208B
8ĆPORT GIGABIT ETHERNET TRANSCEIVER
SLLS578D − AUGUST 2003 − REVISED SEPTEMBER 2006
Table 15. Control Register 4 (0x14) Bit Definitions
BIT(S)
20.15:12
20.11:10
DEFAULT
VALUE = 0x0DBC
NAME
0h
Reserved
11b
PreEmpEF[1:0]
20.9
20.8:0
0b
1 1011 1100b
EdgeOvrCtlEF
IDLE1a[8:0]
DESCRIPTION
Read returns 0s; write is ignored.
Preemphasis control, channels E and F
[00] No preemphasis
[01] Low preemphasis
[10] Mid preemphasis
[11] High preemphasis
Overrides global preemphasis settings for channels E and F when
asserted
First alternate IDLE character. Default is K28.5.
READ/WRITE
Read-only
Read/write
Read/write
Read/write
Table 16. Control Register 5 (0x15) Bit Definitions
BIT(S)
21.15:12
21.11:10
DEFAULT
VALUE = 0x0C50
0h
11b
NAME
Reserved
PreEmpGH[1:0]
21.9
21.8:0
0b
0 0101 0000b
EdgeOvrCtlGH
IDLE2a[8:0]
DESCRIPTION
Read returns 0s; write is ignored.
Preemphasis control, channels G and H
[00] No preemphasis
[01] Low preemphasis
[10] Mid preemphasis
[11] High preemphasis
Overrides global preemphasis settings for channels G and H when
asserted
Second alternate IDLE character. Default is K16.2.
READ/WRITE
Read-only
Read/write
Read/write
Read/write
Table 17. Loopback Control Register (0x16) Bit Definitions
BIT(S)
22.15:8
22.7:0
DEFAULT
VALUE = 0x0000
00h
00h
NAME
LOOPBACK[H:A]
SLOOPBACK[H:A]
DESCRIPTION
READ/WRITE
Serial loopback enable (active high)
Read/write
When asserted high, TX[9:0] data is looped back to RX[9:0], utilizing
the value of the CODE (and 8B/10B_EN) selection to steer the data
path. The serial transmit outputs are held in the high-impedance state
and the serial inputs are ignored.
All bits are logically ORed with the logic value of the LPBK terminal.
Far end loopback enable (active high) channels H:A.
Read/write
Input is received at RX+/RX− inputs, deserialized and steered to
transmit path, and serialized to TX+/TX− outputs.
Note: This is only valid for channel pairs A and B, C and D, E and F
and G and H.
Table 18. Control Register (0x17) Bit Definitions
BIT(S)
23.15:0
DEFAULT
VALUE = 0x0C50
0000h
NAME
Reserved
Read returns 0s.
DESCRIPTION
READ/WRITE
Read-only
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