TLK2208B Datasheet, PDF (18/40 Pages) Texas Instruments – 8-PORT GIGABIT ETHERNET TRANCSEIVER

TLK2208B
8ĆPORT GIGABIT ETHERNET TRANSCEIVER
SLLS578D − AUGUST 2003 − REVISED SEPTEMBER 2006
TERMINAL
NUMBER
U13
U14
U15
U16
U17
TERMINAL
FUNCTION
RDHG8
GNDA
RXA–
RXA+
GNDA
MULTIPLEXED CHANNEL MODE
NIBBLE INTERFACE SYNCHRONIZED AND
INDEPENDENT CHANNEL MODES
Receive bus channel H/G bit 8, K flag
Receive bus channel H bits 8, 3, K-flag
Analog ground
Channel A serial input –
Channel A serial input +
Analog ground
detailed description
reference clock synthesizer
The TLK2208B employs a mature phase-lock loop (PLL) design in use for Gigabit Ethernet transceivers and
high-speed serial links by Texas Instruments since 1997 on both standard products and custom ASIC designs.
This PLL design is used to synthesize the serial line-rate bit clock from the REFCLK input as well as generate
clocks for the receiver sampling circuitry. The PLL and associated high-speed circuitry are powered by the
analog power supply terminals (VDDA) with isolated grounds (GNDA). Care should be taken in providing a
low-noise environment in a system. It is recommended to supply the VDDA reference by a separate isolated
plane within the system printed-circuit board (PCB). It is recommended that systems employing switching power
supplies provide proper filtering of the fundamental and harmonic components in the 2-MHz–10-MHz band to
avoid bit errors from injected noise. It is strongly recommended that no PLL-based clock synthesizer circuit be
used as the source for the REFCLK. This could cause accumulation of jitter between the two PLLs.
operating modes
The TLK2208B has two operational modes selectable via the CODE terminal, as detailed in Table 1.
Table 1. Operational Modes
CODE
OPERATING MODES
Low
SERDES mode. On-chip 8b/10b encoder/decoder is disabled. Refer to the byte alignment logic section, for additional description
on control over this mode.
High
Transceiver mode. Enables 8b/10b encode/decode for each channel. Data on the transmit and receive data buses is treated as
uncoded data. The K-generator bit is used as the K-character generator control. The K-flag is the K-character indicator to the host
device.
NOTE: The logic value of the code terminal is ORed with MDIO register 17.7 (8B/10B_EN).
In SERDES mode, the transmit data bus for each channel accepts 10-bit-wide data on the transmit data channel
terminals. Data is latched on the rising and falling edges of the transmit data clock. The data is then
phase-aligned, serialized, and transmitted sequentially beginning with bit 0 over the differential high-speed
serial transmit terminals. The receive data bus for each channel outputs 10-bit data. Data is output relative to
both the rising and falling edges of the receive clock.
In transceiver mode, the transmit data bus for each channel accepts 8-bit-wide parallel data. Data is sampled
on the rising and falling edges of the transmit clock. The data is first aligned to the reference clock (REFCLK),
then 8b/10b encoded and passed to the serializer. The generation of K-characters on each channel is controlled
by the K-generator bit (see the parallel interface modes section). When the K-generator bit is asserted along
with the 8 bits of data, the appropriate 8b/10b K-character is transmitted. The receive data bus for each channel
outputs 8-bit-wide parallel data. Reception of K-characters is reported on the K-flag bit (see the parallel
interface modes section). When the K-flag of any channel is asserted, the 8 bits of data on that channel’s
receive data bus should be interpreted as a K-character.
When CV_DIS_EN is high, the outputs RDxx[8:0] are set to 1 when a code violation or RD error is detected.
When CV_DIS_EN is low, the outputs RDxx[7:0] are set to 1 when a code violation is detected. An RD error is
not indicated in this case.
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