TLK2208B Datasheet, PDF (28/40 Pages) Texas Instruments – 8-PORT GIGABIT ETHERNET TRANCSEIVER

TLK2208B
8ĆPORT GIGABIT ETHERNET TRANSCEIVER
SLLS578D − AUGUST 2003 − REVISED SEPTEMBER 2006
Table 12. Control Register 1 (0x11) Bit Definitions
BIT(S)
DEFAULT
VALUE= 0x4380
NAME
DESCRIPTION
17.15
0b
TransClkMode
A logic 0 sets all channels synchronous to TCLKB, a logic 1 sets
individual clocking. This register bit is logically ORed with the logic
value of the TCLKSEL input terminal.
17.14
1b
CVDispEn
Code-violation and disparity-error global enable. This bit is logically
ORed with the logic value of the CV_DIS_EN terminal.
17.13:10 0000b
Reserved
Read returns a 0; write is ignored.
17.9
1b
OUT_EN
Global internal parallel output enable (enable = 1).This bit is ANDed
with the logic value of the ENABLE terminal.
17.8
1b
COMMA_DET
Enables comma detect global enable for channel alignment
17.7
1b
8B/10B_EN
Global 8b/10b enable (logically ORed with the logic value of the
CODE terminal)
17.6
0b
MODE_OVR
If set to a logic 1, it permits mode override.
17.5:4 00b
MODE[1:0]
If MODE_OVR is set, permits override of external terminals for mode
setting
17.3
0b
S_RESET
Soft reset (active high). This bit resets all logic in the receive and
transmit sections and in the FIFO. Note that the desertion sequence
of the reset bits is critical to achieving deterministic operation.
Performs similarly to the RESET terminal but does not reset MDIO
registers.
17.2:0 000b
Reserved
Read returns 0s; write is ignored.
NOTE 4: After the S_RESET bit is set to 1, it automatically sets itself back to 0 on the next MDC clock cycle.
READ/WRITE
Read/write
Read/write
Read/write
Read/write
Read/write
Read/write
Read/write
Read/write,
Self-clearing,
See Note 4
Read-only
Table 13. Control Register 2 (0x12) Bit Definitions
BIT(S)
18.15:12
18.11:10
DEFAULT
VALUE = 0x0DBC
NAME
0h
Reserved
11b
PreEmpAB[1:0]
18.9
18.8:0
0b
1 1011 1100b
EdgeOvrCtlAB
IDLE1[8:0]
DESCRIPTION
Read returns 0s; write is ignored.
Preemphasis control, channels A and B
[00] No preemphasis
[01] Low preemphasis
[10] Mid preemphasis
[11] High preemphasis
Overrides global preemphasis settings for channels A and B when
asserted
First IDLE character. Default is K28.5.
READ/WRITE
Read-only
Read/write
Read/write
Read/write
Table 14. Control Register 3 (0x13) Bit Definitions
BIT(S)
19.15:12
19.11:10
DEFAULT
VALUE = 0x0C50
0h
11b
NAME
Reserved
PreEmpCD[1:0]
19.9
0b
19.8:0 0 0101 0000b
EdgeOvrCtlCD
IDLE2[8:0]
DESCRIPTION
Read returns 0s; write is ignored.
Preemphasis control, channels C and D
[00] No preemphasis
[01] Low preemphasis
[10] Mid preemphasis
[11] High preemphasis
Overrides global preemphasis settings for channels C and D when
asserted
Second IDLE character. Default is D16.2.
READ/WRITE
Read-only
Read/write
Read/write
Read/write
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