TLK2208B Datasheet, PDF (7/40 Pages) Texas Instruments – 8-PORT GIGABIT ETHERNET TRANCSEIVER

TLK2208B
8ĆPORT GIGABIT ETHERNET TRANSCEIVER
SLLS578D − AUGUST 2003 − REVISED SEPTEMBER 2006
SIGNAL
TDHG8
TDHG9
LOCATION
A13
B13
TYPE
LVCMOS
input
LVCMOS
input with
P/D
DESCRIPTION
Transmit data, K-generator channels G and H. In multiplexed channel mode, when CODE = low, this
terminal is the 9th bit of a 10-bit word to be transmitted. When CODE = high, this terminal acts as the
K-character indicator. When TDHG8 = high, the data on TDHG[7:0] is encoded into a K-character.
In nibble interface mode, when CODE = low, this terminal is the 4th and 9th bits of a 10-bit word to be
transmitted on channel H. When CODE = high, this terminal acts as the K-character indicator for
channel H.
In independent channel mode, the transmit clock that latches this input is TCLKH. In all other modes,
the transmit clock is TCLKB.
Transmit data channels G and H. When CODE = low, this terminal is the 10th bit of a 10-bit word. When
CODE = high, this terminal should be left floating or tied low to ground.
In independent channel mode, the transmit clock that latches this input is TCLKH. In all other modes,
the transmit clock is TCLKB.
Receive Data Bus and Clock Signals
SIGNAL
RCLK/
RBCH
RBC[G:A]
RDBA[7:0]
RDBA8
LOCATION
R10
R9, R8, R7,
R6, R5, R4,
P4
N2, N1,
M2, M1, L2,
L1, K2, K1
P1
TYPE
DESCRIPTION
LVCMOS
output
Receive byte clock. In synchronized channel modes (nibble mode or multiplexed channel mode), RCLK
is a buffered version of REFCLK used by the protocol device to latch the received data output on
RDBA[9:0], RDDC[9:0], RDFE[9:0] and RDHG[9:0].
With the internal CTC FIFO disabled (only valid for nibble interface mode), this clock is 1/10th the clock
recovered from the incoming data stream. If CTC is enabled, this clock is a buffered version of REFCLK.
This terminal is internally series-terminated to provide direct connection to a 50-Ω transmission line.
LVCMOS
output
Individual receive byte clock channels A through G. Recovered clock for channels A through G.
When in independent channel mode, these clocks are used by the protocol device to latch the received
data output for channels A through G. Data is aligned to both the rising and falling edges. When in nibble
interface mode with the internal CTC FIFO disabled, these terminals are 1/10th the clock recovered from
the incoming data stream. If CTC is enabled, these clocks are all buffered versions of REFCLK.
When in multiplexed channel mode, the RBCG clock becomes a complementary output to
RCLK/RBCH. Similarly, RBCB and RBCA, RBCD and RBCC, RBCF and RBCE are paired clock copies
of RCLK/RBCH and RBCG.
These terminals are internally series-terminated to provide direct connection to a 50-Ω transmission
line.
LVCMOS Receive data channels A and B. The parallel data is clocked out of the transceiver on the rising and
output falling edges of the receive clock.
In multiplexed channel mode, data for channel B is aligned to the rising edge of RCLK and data for
channel A is aligned to the falling edge of RCLK (see Figure 6 for clarity).
In nibble mode, data is output least-significant nibble first, aligned to the falling edge of the receive clock,
followed by the most-significant nibble aligned to the rising edge. Channel A is output on RDBA[4:0]
and channel B is output on RDBA[9:5]. When CODE = high, RDBA3 acts as the K-flag bit for channel
A on the rising edge of RCLK.
These terminals are internally series-terminated to provide direct connection to a 50-Ω transmission
line.
LVCMOS
output
Receive data/K-flag, channels A and B. The parallel data is clocked out of the transceiver on the rising
and falling edges of the receive clock.
In multiplexed channel mode, when CODE = low, this terminal is the 9th bit of a 10-bit word received.
When CODE = high, this terminal acts as the K-flag bit. When RDBA8 = high, this terminal indicates
that the data on RDBA[7:0] is a K-character.
In nibble interface mode, when CODE = low, this terminal is the 4th and 9th bits of a 10-bit word received
on channel B. When CODE = high, this terminal acts as the 4th bit on the falling edge and as the K-flag
bit on the rising edge for channel B. When RDBA8 = high, this terminal indicates that the data on
RDBA[7:0], output on the rising and falling edges of the receive clock, is a K-character.
This terminal is internally series-terminated to provide direct connection to a 50-Ω transmission line.
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